Pass ECP5 fpga and jlink debug core.

example_soc/soc/example_soc.v

@@ -18,7 +18,7 @@ module example_soc #(
 	// System clock + reset
 	input wire               clk,
 	input wire               rst_n,
-	output reg               led_o,
+	output wire               led_o,
 
 	// JTAG port to RISC-V JTAG-DTM
 	input  wire              tck,
@@ -56,14 +56,13 @@ reg  [31:0]       dmi_prdata;
 wire              dmi_pready;
 wire              dmi_pslverr;
 
-
 reg  [31:0] cpt_s;
 wire [31:0] cpt_next_s = cpt_s + 1'b1;
+assign led_o = cpt_s[22];
 
 always @(posedge clk) begin
-	if (!rst_n) begin
+	if (rst_n) begin
 	  cpt_s <= cpt_next_s;
-		led_o <= cpt_s[16];
 	end
 end
 

test/sim/hellow/main.c

@@ -16,8 +16,8 @@ int main() {
   uart_wait_done();
 
   // tb_puts("Hello world from Hazard3 + CXXRTL!\n");
-  uint32_t addr = 0x40008000;
-  uint32_t *point = (uint32_t *)addr;
-  *point = 'C';
+  // uint32_t addr = 0x40008000;
+  // uint32_t *point = (uint32_t *)addr;
+  // *point = 'C';
   return 123;
 }

test/sim/soc_cxxrtl/Makefile

@@ -34,18 +34,18 @@ synth: $(FILE_LIST) $(wildcard *.vh)
 	yosys -p '$(SYNTH_CMD)'
 
 nextpnr:
-	nextpnr-ecp5 --25k --package CABGA381 --speed 6 --lpf-allow-unconstrained --textcfg $(BUILD_DIR)/soc.cfg --lpf soc.lpf --freq 12  --json $(BUILD_DIR)/soc.json
+	nextpnr-ecp5 --25k --package CABGA381 --speed 6 --lpf-allow-unconstrained --textcfg $(BUILD_DIR)/soc.cfg --lpf soc.lpf --freq 25  --json $(BUILD_DIR)/soc.json
 
 $(BUILD_DIR)/soc.bit: $(BUILD_DIR)/soc.cfg
 	ecppack --svf $(BUILD_DIR)/soc.svf ./$< ./$@
 
 $(BUILD_DIR)/soc.svf : $(BUILD_DIR)/soc.bit
 
-prog: $(BUILD_DIR)/soc.svf
-	ecpdap program $(BUILD_DIR)/soc.svf
+prog: $(BUILD_DIR)/soc.bit
+	ecpdap program $(BUILD_DIR)/soc.bit
 
 flash: $(BUILD_DIR)/soc.bit
-	ecpdap flash write $(BUILD_DIR)/soc.svf
+	ecpdap flash write $(BUILD_DIR)/soc.bit
 
 
 CXXRTL_CMD += read_verilog -I ../../../hdl -DCONFIG_HEADER="config_$(CONFIG).vh" $(FILE_LIST);
@@ -65,6 +65,9 @@ sim: $(TBEXEC)
 openocd:
 	openocd -f openocd.cfg
 
+jlink:
+	openocd -f openocd-jlink.cfg
+
 gdb:
 	/opt/riscv/bin/riscv32-unknown-elf-gdb -x gdb_init
 

test/sim/soc_cxxrtl/openocd-jlink.cfg

@@ -0,0 +1,15 @@
+
+adapter driver jlink
+transport select jtag
+adapter speed 2000
+
+transport select jtag
+
+set _CHIPNAME hazard3
+jtag newtap $_CHIPNAME cpu -irlen 5
+set _TARGETNAME $_CHIPNAME.cpu
+target create $_TARGETNAME riscv -chain-position $_TARGETNAME
+
+gdb_report_data_abort enable
+init
+halt

test/sim/soc_cxxrtl/soc.lpf

@@ -5,7 +5,7 @@ FREQUENCY PORT "clk" 25 MHZ;
 
 LOCATE COMP "led_o" SITE "U16";
 IOBUF PORT "led_o" IO_TYPE=LVCMOS33;
-FREQUENCY PORT "led_o" 25 MHZ;
+
 
 LOCATE COMP "rst_n" SITE "B19";
 IOBUF PORT "rst_n" PULLMODE=UP IO_TYPE=LVCMOS33;