colin
/
Hazard3
1
0
Fork 0
Code Issues Pull Requests Packages Projects Releases Wiki Activity

Add led output, refine io plan.

This commit is contained in:
Colin 2025-04-01 18:11:04 +08:00
parent bf0e102e90
commit b188194887
2 changed files with 22 additions and 8 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

11
example_soc/soc/example_soc.v
View File

@ -18,6 +18,7 @@ module example_soc #(
// System clock + reset
input wire clk,
input wire rst_n,
output reg led_o,
// JTAG port to RISC-V JTAG-DTM
input wire tck,
@ -56,6 +57,16 @@ wire dmi_pready;
wire dmi_pslverr;
reg [31:0] cpt_s;
wire [31:0] cpt_next_s = cpt_s + 1'b1;
always @(posedge clk) begin
if (!rst_n) begin
cpt_s <= cpt_next_s;
led_o <= cpt_s[16];
end
end
// TCK-domain DTM logic can force a hard reset
wire dmihardreset_req;
wire assert_dmi_reset = !rst_n || dmihardreset_req;

19
test/sim/soc_cxxrtl/soc.lpf
View File

@ -3,16 +3,18 @@ LOCATE COMP "clk" SITE "P3";
IOBUF PORT "clk" IO_TYPE=LVCMOS33;
FREQUENCY PORT "clk" 25 MHZ;
LOCATE COMP "trst_n" SITE "D20";
IOBUF PORT "trst_n" IO_TYPE=LVCMOS33;
FREQUENCY PORT "trst_n" 25 MHZ;
LOCATE COMP "led_o" SITE "U16";
IOBUF PORT "led_o" IO_TYPE=LVCMOS33;
FREQUENCY PORT "led_o" 25 MHZ;
LOCATE COMP "rst_n" SITE "B19";
IOBUF PORT "rst_n" IO_TYPE=LVCMOS33;
IOBUF PORT "rst_n" PULLMODE=UP IO_TYPE=LVCMOS33;
FREQUENCY PORT "rst_n" 25 MHZ;
LOCATE COMP "trst_n" SITE "H5";
IOBUF PORT "trst_n" PULLMODE=UP IO_TYPE=LVCMOS33;
FREQUENCY PORT "trst_n" 25 MHZ;
LOCATE COMP "tdi" SITE "E1";
IOBUF PORT "tdi" IO_TYPE=LVCMOS33;
@ -30,9 +32,10 @@ IOBUF PORT "tms" IO_TYPE=LVCMOS33;
FREQUENCY PORT "tms" 25 MHZ;
LOCATE COMP "uart_rx" SITE "J5";
LOCATE COMP "uart_rx" SITE "D20";
IOBUF PORT "uart_rx" IO_TYPE=LVCMOS33;
FREQUENCY PORT "uart_rx" 25 MHZ;
LOCATE COMP "uart_tx" SITE "U16";
IOBUF PORT "uart_tx" IO_TYPE=LVCMOS33;
LOCATE COMP "uart_tx" SITE "F20";
IOBUF PORT "uart_tx" IO_TYPE=LVCMOS33;
FREQUENCY PORT "uart_tx" 25 MHZ;