Refine tb main.
This commit is contained in:
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aaad0d85a5
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393499537d
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@ -44,231 +44,6 @@ enum {
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IO_MTIMECMP1H = 0x114
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};
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// struct mem_io_state {
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// uint64_t mtime;
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// uint64_t mtimecmp[2];
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// bool exit_req;
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// uint32_t exit_code;
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// uint8_t *mem;
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// bool monitor_enabled;
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// bool reservation_valid[2];
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// uint32_t reservation_addr[2];
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// mem_io_state() {
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// mtime = 0;
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// mtimecmp[0] = 0;
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// mtimecmp[1] = 0;
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// exit_req = false;
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// exit_code = 0;
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// monitor_enabled = false;
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// for (int i = 0; i < N_RESERVATIONS; ++i) {
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// reservation_valid[i] = false;
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// reservation_addr[i] = 0;
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// }
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// mem = new uint8_t[MEM_SIZE];
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// for (size_t i = 0; i < MEM_SIZE; ++i)
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// mem[i] = 0;
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// }
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// Where we're going we don't need a destructor B-)
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// void step(cxxrtl_design::p_example__soc &tb) {
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// // Default update logic for mtime, mtimecmp
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// ++mtime;
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// // tb.p_timer__irq.set<uint8_t>((mtime >= mtimecmp[0]) | (mtime
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// >= mtimecmp[1]) << 1);
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// }
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// };
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// typedef enum {
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// SIZE_BYTE = 0,
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// SIZE_HWORD = 1,
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// SIZE_WORD = 2
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// } bus_size_t;
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// struct bus_request {
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// uint32_t addr;
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// bus_size_t size;
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// bool write;
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// bool excl;
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// uint32_t wdata;
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// int reservation_id;
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// bus_request(): addr(0), size(SIZE_BYTE), write(0), excl(0), wdata(0),
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// reservation_id(0) {}
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// };
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// struct bus_response {
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// uint32_t rdata;
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// int stall_cycles;
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// bool err;
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// bool exokay;
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// bus_response(): rdata(0), stall_cycles(0), err(false), exokay(true) {}
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// };
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// bus_response mem_access(cxxrtl_design::p_example__soc &tb, mem_io_state
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// &memio, bus_request req) { bus_response resp;
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// // Global monitor. When monitor is not enabled, HEXOKAY is tied high
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// if (memio.monitor_enabled) {
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// if (req.excl) {
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// // Always set reservation on read. Always clear
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// reservation on
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// // write. On successful write, clear others' matching
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// reservations. if (req.write) {
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// resp.exokay = memio.reservation_valid[req.reservation_id] &&
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// memio.reservation_addr[req.reservation_id]
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// == (req.addr & RESERVATION_ADDR_MASK);
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// memio.reservation_valid[req.reservation_id] =
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// false; if (resp.exokay) {
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// for (int i = 0; i < N_RESERVATIONS; ++i) {
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// if (i == req.reservation_id)
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// continue; if
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// (memio.reservation_addr[i] == (req.addr & RESERVATION_ADDR_MASK))
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// memio.reservation_valid[i] = false;
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// }
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// }
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// }
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// else {
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// resp.exokay = true;
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// memio.reservation_valid[req.reservation_id] =
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// true;
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// memio.reservation_addr[req.reservation_id] = req.addr &
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// RESERVATION_ADDR_MASK;
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// }
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// }
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// else {
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// resp.exokay = false;
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// // Non-exclusive write still clears others' reservations
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// if (req.write) {
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// for (int i = 0; i < N_RESERVATIONS; ++i) {
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// if (i == req.reservation_id)
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// continue;
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// if (memio.reservation_addr[i] ==
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// (req.addr & RESERVATION_ADDR_MASK))
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// memio.reservation_valid[i] = false;
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// }
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// }
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// }
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// }
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// if (req.write) {
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// if (memio.monitor_enabled && req.excl && !resp.exokay) {
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// // Failed exclusive write; do nothing
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// }
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// else if (req.addr <= MEM_SIZE - 4u) {
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// unsigned int n_bytes = 1u << (int)req.size;
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// // Note we are relying on hazard3's byte lane
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// replication for (unsigned int i = 0; i < n_bytes; ++i) {
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// memio.mem[req.addr + i] = req.wdata >> (8 * i) & 0xffu;
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// }
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// }
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// else if (req.addr == IO_BASE + IO_PRINT_CHAR) {
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// putchar(req.wdata);
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// }
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// else if (req.addr == IO_BASE + IO_PRINT_U32) {
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// printf("%08x\n", req.wdata);
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// }
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// else if (req.addr == IO_BASE + IO_EXIT) {
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// if (!memio.exit_req) {
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// memio.exit_req = true;
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// memio.exit_code = req.wdata;
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// }
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// }
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// else if (req.addr == IO_BASE + IO_SET_SOFTIRQ) {
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// //
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// tb.p_soft__irq.set<uint8_t>(tb.p_soft__irq.get<uint8_t>() | req.wdata);
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// }
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// else if (req.addr == IO_BASE + IO_CLR_SOFTIRQ) {
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// //
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// tb.p_soft__irq.set<uint8_t>(tb.p_soft__irq.get<uint8_t>() & ~req.wdata);
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// }
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// else if (req.addr == IO_BASE + IO_GLOBMON_EN) {
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// memio.monitor_enabled = req.wdata;
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// }
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// else if (req.addr == IO_BASE + IO_SET_IRQ) {
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// // tb.p_irq.set<uint32_t>(tb.p_irq.get<uint32_t>() |
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// req.wdata);
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// }
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// else if (req.addr == IO_BASE + IO_CLR_IRQ) {
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// // tb.p_irq.set<uint32_t>(tb.p_irq.get<uint32_t>() &
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// ~req.wdata);
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// }
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// else if (req.addr == IO_BASE + IO_MTIME) {
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// memio.mtime = (memio.mtime & 0xffffffff00000000u) |
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// req.wdata;
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// }
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// else if (req.addr == IO_BASE + IO_MTIMEH) {
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// memio.mtime = (memio.mtime & 0x00000000ffffffffu) |
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// ((uint64_t)req.wdata << 32);
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// }
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// else if (req.addr == IO_BASE + IO_MTIMECMP0) {
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// memio.mtimecmp[0] = (memio.mtimecmp[0] &
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// 0xffffffff00000000u) | req.wdata;
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// }
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// else if (req.addr == IO_BASE + IO_MTIMECMP0H) {
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// memio.mtimecmp[0] = (memio.mtimecmp[0] &
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// 0x00000000ffffffffu) | ((uint64_t)req.wdata << 32);
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// }
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// else if (req.addr == IO_BASE + IO_MTIMECMP1) {
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// memio.mtimecmp[1] = (memio.mtimecmp[1] &
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// 0xffffffff00000000u) | req.wdata;
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// }
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// else if (req.addr == IO_BASE + IO_MTIMECMP1H) {
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// memio.mtimecmp[1] = (memio.mtimecmp[1] &
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// 0x00000000ffffffffu) | ((uint64_t)req.wdata << 32);
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// }
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// else {
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// resp.err = true;
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// }
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// }
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// else {
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// if (req.addr <= MEM_SIZE - (1u << (int)req.size)) {
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// req.addr &= ~0x3u;
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// resp.rdata =
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// (uint32_t)memio.mem[req.addr] |
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// memio.mem[req.addr + 1] << 8 |
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// memio.mem[req.addr + 2] << 16 |
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// memio.mem[req.addr + 3] << 24;
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// }
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// else if (req.addr == IO_BASE + IO_SET_SOFTIRQ || req.addr ==
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// IO_BASE + IO_CLR_SOFTIRQ) {
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// // resp.rdata = tb.p_soft__irq.get<uint8_t>();
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// }
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// else if (req.addr == IO_BASE + IO_SET_IRQ || req.addr == IO_BASE
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// + IO_CLR_IRQ) {
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// // resp.rdata = tb.p_irq.get<uint32_t>();
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// }
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// else if (req.addr == IO_BASE + IO_MTIME) {
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// resp.rdata = memio.mtime;
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// }
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// else if (req.addr == IO_BASE + IO_MTIMEH) {
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// resp.rdata = memio.mtime >> 32;
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// }
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// else if (req.addr == IO_BASE + IO_MTIMECMP0) {
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// resp.rdata = memio.mtimecmp[0];
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// }
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// else if (req.addr == IO_BASE + IO_MTIMECMP0H) {
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// resp.rdata = memio.mtimecmp[0] >> 32;
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// }
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// else if (req.addr == IO_BASE + IO_MTIMECMP1) {
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// resp.rdata = memio.mtimecmp[1];
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// }
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// else if (req.addr == IO_BASE + IO_MTIMECMP1H) {
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// resp.rdata = memio.mtimecmp[1] >> 32;
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// }
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// else {
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// resp.err = true;
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// }
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// }
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// if (resp.err) {
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// resp.exokay = false;
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// }
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// return resp;
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// }
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// -----------------------------------------------------------------------------
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const char *help_str =
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@ -425,23 +200,6 @@ int main(int argc, char **argv) {
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server_fd, port, (struct sockaddr *)&sock_addr, &sock_addr_len);
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}
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// mem_io_state memio;
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// if (load_bin) {
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// std::ifstream fd(bin_path, std::ios::binary | std::ios::ate);
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// if (!fd){
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// std::cerr << "Failed to open \"" << bin_path << "\"\n";
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// return -1;
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// }
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// std::streamsize bin_size = fd.tellg();
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// if (bin_size > MEM_SIZE) {
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// std::cerr << "Binary file (" << bin_size << " bytes) is larger
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// than memory (" << MEM_SIZE << " bytes)\n"; return -1;
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// }
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// fd.seekg(0, std::ios::beg);
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// fd.read((char*)memio.mem, bin_size);
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// }
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std::ofstream jtag_dump_fd;
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if (dump_jtag) {
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jtag_dump_fd.open(jtag_dump_path);
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@ -472,20 +230,6 @@ int main(int argc, char **argv) {
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vcd.add(all_debug_items);
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}
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// Loop-carried address-phase requests
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// bus_request req_i;
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// bus_request req_d;
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// bool req_i_vld = false;
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// bool req_d_vld = false;
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// req_i.reservation_id = 0;
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// req_d.reservation_id = 1;
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// Set bus interfaces to generate good IDLE responses at first
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// top.p_i__hready.set<bool>(true);
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// top.p_d__hready.set<bool>(true);
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// Reset + initial clock pulse
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top.step();
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top.p_clk.set<bool>(true);
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top.p_tck.set<bool>(true);
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@ -591,78 +335,6 @@ int main(int argc, char **argv) {
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}
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}
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// memio.step(top);
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// The two bus ports are handled identically. This enables swapping out of
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// various `tb.v` hardware integration files containing:
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//
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// - A single, dual-ported processor (instruction fetch, load/store ports)
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// - A single, single-ported processor (instruction fetch + load/store muxed
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// internally)
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// - A pair of single-ported processors, for dual-core debug tests
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// if (top.p_d__hready.get<bool>()) {
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// // Clear bus error by default
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// top.p_d__hresp.set<bool>(false);
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// // Handle current data phase
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// req_d.wdata = top.p_d__hwdata.get<uint32_t>();
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// bus_response resp;
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// if (req_d_vld)
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// resp = mem_access(top, memio, req_d);
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// else
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// resp.exokay = !memio.monitor_enabled;
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// if (resp.err) {
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// // Phase 1 of error response
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// top.p_d__hready.set<bool>(false);
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// top.p_d__hresp.set<bool>(true);
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// }
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// top.p_d__hrdata.set<uint32_t>(resp.rdata);
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// top.p_d__hexokay.set<bool>(resp.exokay);
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// // Progress current address phase to data phase
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// req_d_vld = top.p_d__htrans.get<uint8_t>() >> 1;
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// req_d.write = top.p_d__hwrite.get<bool>();
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// req_d.size = (bus_size_t)top.p_d__hsize.get<uint8_t>();
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// req_d.addr = top.p_d__haddr.get<uint32_t>();
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// req_d.excl = top.p_d__hexcl.get<bool>();
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// }
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// else {
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// // hready=0. Currently this only happens when we're in the first
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// // phase of an error response, so go to phase 2.
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// top.p_d__hready.set<bool>(true);
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// }
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// if (top.p_i__hready.get<bool>()) {
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// top.p_i__hresp.set<bool>(false);
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// req_i.wdata = top.p_i__hwdata.get<uint32_t>();
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// bus_response resp;
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// if (req_i_vld)
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// resp = mem_access(top, memio, req_i);
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// else
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// resp.exokay = !memio.monitor_enabled;
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// if (resp.err) {
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// // Phase 1 of error response
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// top.p_i__hready.set<bool>(false);
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// top.p_i__hresp.set<bool>(true);
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// }
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// top.p_i__hrdata.set<uint32_t>(resp.rdata);
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// top.p_i__hexokay.set<bool>(resp.exokay);
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// // Progress current address phase to data phase
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// req_i_vld = top.p_i__htrans.get<uint8_t>() >> 1;
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// req_i.write = top.p_i__hwrite.get<bool>();
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// req_i.size = (bus_size_t)top.p_i__hsize.get<uint8_t>();
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// req_i.addr = top.p_i__haddr.get<uint32_t>();
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// req_i.excl = top.p_i__hexcl.get<bool>();
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// }
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// else {
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// // hready=0. Currently this only happens when we're in the first
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// // phase of an error response, so go to phase 2.
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// top.p_i__hready.set<bool>(true);
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// }
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if (dump_waves) {
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// The extra step() is just here to get the bus responses to line up
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// nicely in the VCD (hopefully is a quick update)
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@ -672,11 +344,6 @@ int main(int argc, char **argv) {
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vcd.buffer.clear();
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}
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// if (memio.exit_req) {
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// printf("CPU requested halt. Exit code %d\n", memio.exit_code);
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// printf("Ran for " I64_FMT " cycles\n", cycle + 1);
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// break;
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// }
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if (cycle + 1 == max_cycles) {
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printf("Max cycles reached\n");
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timed_out = true;
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@ -692,20 +359,9 @@ int main(int argc, char **argv) {
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jtag_replay_fd.close();
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}
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// for (auto r : dump_ranges) {
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// printf("Dumping memory from %08x to %08x:\n", r.first, r.second);
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// for (int i = 0; i < r.second - r.first; ++i)
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// printf("%02x%c", memio.mem[r.first + i], i % 16 == 15 ? '\n' : '
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// '); printf("\n");
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// }
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if (propagate_return_code && timed_out) {
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return -1;
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}
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// else if (propagate_return_code && memio.exit_req) {
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// return memio.exit_code;
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// }
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else {
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} else {
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return 0;
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}
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}
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