Enable aph port off soc, and print prints.

example_soc/soc/example_soc.v

@@ -28,7 +28,16 @@ module example_soc #(
 
 	// IO
 	output wire              uart_tx,
-	input  wire              uart_rx
+	input  wire              uart_rx,
+
+	output wire        gp_psel,
+	output wire        gp_penable,
+	output wire        gp_pwrite,
+	output wire [15:0] gp_paddr,
+	output wire [31:0] gp_pwdata,
+	input wire [31:0]  gp_prdata,
+	input wire         gp_pready,
+	input wire         gp_pslverr,
 );
 
 localparam W_ADDR = 32;
@@ -346,9 +355,10 @@ hazard3_cpu_1port #(
 // ----------------------------------------------------------------------------
 // Bus fabric
 
-// - 128 kB SRAM at... 0x0000_0000
-// - System timer at.. 0x4000_0000
-// - UART at.......... 0x4000_4000
+// - 128 kB SRAM at... 0x0000_0000  Mask:  0xe0000000
+// - System timer at.. 0x4000_0000  Mask:  0xe000c000
+// - UART at.......... 0x4000_4000  Mask:  0xe000c000
+// - GP   at.......... 0x4000_8000  Mask:  0xe000c000
 
 // AHBL layer
 
@@ -470,9 +480,9 @@ ahbl_to_apb apb_bridge_u (
 );
 
 apb_splitter #(
-	.N_SLAVES   (2),
-	.ADDR_MAP   (32'h4000_0000),
-	.ADDR_MASK  (32'hc000_c000)
+	.N_SLAVES   (3),
+	.ADDR_MAP   (48'h4000_0000_8000),
+	.ADDR_MASK  (48'hc000_c000_c000)
 ) inst_apb_splitter (
 	.apbs_paddr   (bridge_paddr),
 	.apbs_psel    (bridge_psel),
@@ -483,14 +493,14 @@ apb_splitter #(
 	.apbs_prdata  (bridge_prdata),
 	.apbs_pslverr (bridge_pslverr),
 
-	.apbm_paddr   ({uart_paddr   , timer_paddr  }),
-	.apbm_psel    ({uart_psel    , timer_psel   }),
-	.apbm_penable ({uart_penable , timer_penable}),
-	.apbm_pwrite  ({uart_pwrite  , timer_pwrite }),
-	.apbm_pwdata  ({uart_pwdata  , timer_pwdata }),
-	.apbm_pready  ({uart_pready  , timer_pready }),
-	.apbm_prdata  ({uart_prdata  , timer_prdata }),
-	.apbm_pslverr ({uart_pslverr , timer_pslverr})
+	.apbm_paddr   ({uart_paddr   , timer_paddr,   gp_paddr  }),
+	.apbm_psel    ({uart_psel    , timer_psel,    gp_psel   }),
+	.apbm_penable ({uart_penable , timer_penable, gp_penable}),
+	.apbm_pwrite  ({uart_pwrite  , timer_pwrite,  gp_pwrite }),
+	.apbm_pwdata  ({uart_pwdata  , timer_pwdata,  gp_pwdata }),
+	.apbm_pready  ({uart_pready  , timer_pready,  gp_pready }),
+	.apbm_prdata  ({uart_prdata  , timer_prdata,  gp_prdata }),
+	.apbm_pslverr ({uart_pslverr , timer_pslverr, gp_pslverr})
 );
 
 // ----------------------------------------------------------------------------

test/sim/common/tb_cxxrtl_io.h

@@ -9,7 +9,7 @@
 // ----------------------------------------------------------------------------
 // Testbench IO hardware layout
 
-#define IO_BASE 0x40000000
+#define IO_BASE 0x40008000
 
 typedef struct {
 	volatile uint32_t print_char;

test/sim/hellow/main.c

@@ -1,6 +1,12 @@
 #include "tb_cxxrtl_io.h"
-
-int main() {
-	tb_puts("Hello world from Hazard3 + CXXRTL!\n");
-	return 123;
+__attribute__((optimize("O0"))) int main() {
+  // tb_puts("Hello world from Hazard3 + CXXRTL!\n");
+  uint32_t addr = 0x40008000;
+  uint32_t *point = (uint32_t *)addr;
+  *point = 'C';
+  *point = 'O';
+  *point = 'L';
+  *point = 'I';
+  *point = 'N';
+  return 123;
 }