colin
/
Hazard3
1
0
Fork 0
Code Issues Pull Requests Packages Projects Releases Wiki Activity

Example soc: connect up power signals and always-on clock. Set more parameters explicitly.

This commit is contained in:
Luke Wren 2022-09-04 23:42:48 +01:00
parent 624d39669d
commit 3ae843034d
2 changed files with 67 additions and 28 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

19
example_soc/fpga/fpga_icebreaker.v
View File

@ -65,13 +65,26 @@ example_soc #(
.EXTENSION_A (1), .EXTENSION_A (1),
.EXTENSION_C (0), .EXTENSION_C (0),
.EXTENSION_M (1), .EXTENSION_M (1),
.MUL_FAST (0),
.MULH_FAST (0),
.EXTENSION_ZBA (0), .EXTENSION_ZBA (0),
.EXTENSION_ZBB (0), .EXTENSION_ZBB (0),
.EXTENSION_ZBC (0), .EXTENSION_ZBC (0),
.EXTENSION_ZBS (0), .EXTENSION_ZBS (0),
.CSR_COUNTER (0) .EXTENSION_ZBKB (0),
.EXTENSION_ZIFENCEI (0),
.EXTENSION_XH3BEXTM (0),
.EXTENSION_XH3POWER (0),
.CSR_COUNTER (0),
.U_MODE (0),
.PMP_REGIONS (0),
.BREAKPOINT_TRIGGERS (0),
.IRQ_PRIORITY_BITS (0),
.REDUCED_BYPASS (0),
.MULDIV_UNROLL (1),
.MUL_FAST (0),
.MUL_FASTER (0),
.MULH_FAST (0),
.FAST_BRANCHCMP (1),
.BRANCH_PREDICTOR (0)
) soc_u ( ) soc_u (
.clk (clk_sys), .clk (clk_sys),
.rst_n (rst_n_sys), .rst_n (rst_n_sys),

28
example_soc/soc/example_soc.v
View File

@ -235,12 +235,15 @@ wire proc_hexokay = 1'b1; // No global monitor
wire [W_DATA-1:0] proc_hwdata; wire [W_DATA-1:0] proc_hwdata;
wire [W_DATA-1:0] proc_hrdata; wire [W_DATA-1:0] proc_hrdata;
wire pwrup_req;
wire unblock_out;
wire uart_irq; wire uart_irq;
wire timer_irq; wire timer_irq;
hazard3_cpu_1port #( hazard3_cpu_1port #(
// These must have the values given here for you to end up with a useful SoC: // These must have the values given here for you to end up with a useful SoC:
.RESET_VECTOR (32'h0000_00c0), .RESET_VECTOR (32'h0000_0040),
.MTVEC_INIT (32'h0000_0000), .MTVEC_INIT (32'h0000_0000),
.CSR_M_MANDATORY (1), .CSR_M_MANDATORY (1),
.CSR_M_TRAP (1), .CSR_M_TRAP (1),
@ -256,18 +259,41 @@ hazard3_cpu_1port #(
.EXTENSION_ZBB (EXTENSION_ZBB), .EXTENSION_ZBB (EXTENSION_ZBB),
.EXTENSION_ZBC (EXTENSION_ZBC), .EXTENSION_ZBC (EXTENSION_ZBC),
.EXTENSION_ZBS (EXTENSION_ZBS), .EXTENSION_ZBS (EXTENSION_ZBS),
.EXTENSION_ZBKB (EXTENSION_ZBKB),
.EXTENSION_ZIFENCEI (EXTENSION_ZIFENCEI),
.EXTENSION_XH3BEXTM (EXTENSION_XH3BEXTM),
.EXTENSION_XH3POWER (EXTENSION_XH3POWER),
.CSR_COUNTER (CSR_COUNTER), .CSR_COUNTER (CSR_COUNTER),
.U_MODE (U_MODE),
.PMP_REGIONS (PMP_REGIONS),
.PMP_GRAIN (PMP_GRAIN),
.PMP_HARDWIRED (PMP_HARDWIRED),
.PMP_HARDWIRED_ADDR (PMP_HARDWIRED_ADDR),
.PMP_HARDWIRED_CFG (PMP_HARDWIRED_CFG),
.MVENDORID_VAL (MVENDORID_VAL), .MVENDORID_VAL (MVENDORID_VAL),
.BREAKPOINT_TRIGGERS (BREAKPOINT_TRIGGERS),
.IRQ_PRIORITY_BITS (IRQ_PRIORITY_BITS),
.MIMPID_VAL (MIMPID_VAL), .MIMPID_VAL (MIMPID_VAL),
.MHARTID_VAL (MHARTID_VAL), .MHARTID_VAL (MHARTID_VAL),
.REDUCED_BYPASS (REDUCED_BYPASS), .REDUCED_BYPASS (REDUCED_BYPASS),
.MULDIV_UNROLL (MULDIV_UNROLL), .MULDIV_UNROLL (MULDIV_UNROLL),
.MUL_FAST (MUL_FAST), .MUL_FAST (MUL_FAST),
.MUL_FASTER (MUL_FASTER),
.MULH_FAST (MULH_FAST),
.FAST_BRANCHCMP (FAST_BRANCHCMP),
.BRANCH_PREDICTOR (BRANCH_PREDICTOR),
.MTVEC_WMASK (MTVEC_WMASK) .MTVEC_WMASK (MTVEC_WMASK)
) cpu ( ) cpu (
.clk (clk), .clk (clk),
.clk_always_on (clk),
.rst_n (rst_n_cpu), .rst_n (rst_n_cpu),
.pwrup_req (pwrup_req),
.pwrup_ack (pwrup_req), // Tied back
.clk_en (/* unused */),
.unblock_out (unblock_out),
.unblock_in (unblock_out), // Tied back
.haddr (proc_haddr), .haddr (proc_haddr),
.hwrite (proc_hwrite), .hwrite (proc_hwrite),
.htrans (proc_htrans), .htrans (proc_htrans),