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Revise default config values, and update docs with new values

This commit is contained in:
Luke Wren 2022-10-08 08:43:25 +01:00
parent 0b18fae32e
commit 489480dc80
3 changed files with 4237 additions and 4087 deletions
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8220
doc/hazard3.pdf
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61
doc/sections/configuration_and_integration.adoc
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@ -73,28 +73,28 @@ Default value: 1
Support for Zba address generation instructions. 0 for disable, 1 for enable. Support for Zba address generation instructions. 0 for disable, 1 for enable.
Default value: 1 Default value: 0
[[param-EXTENSION_ZBB]] [[param-EXTENSION_ZBB]]
===== EXTENSION_ZBB ===== EXTENSION_ZBB
Support for Zbb basic bit manipulation instructions. 0 for disable, 1 for enable. Support for Zbb basic bit manipulation instructions. 0 for disable, 1 for enable.
Default value: 1 Default value: 0
[[param-EXTENSION_ZBC]] [[param-EXTENSION_ZBC]]
===== EXTENSION_ZBC ===== EXTENSION_ZBC
Support for Zbc carry-less multiplication instructions. 0 for disable, 1 for enable. Support for Zbc carry-less multiplication instructions. 0 for disable, 1 for enable.
Default value: 1 Default value: 0
[[param-EXTENSION_ZBS]] [[param-EXTENSION_ZBS]]
===== EXTENSION_ZBS ===== EXTENSION_ZBS
Support for Zbs single-bit manipulation instructions. 0 for disable, 1 for enable. Support for Zbs single-bit manipulation instructions. 0 for disable, 1 for enable.
Default value: 1 Default value: 0
[[param-EXTENSION_ZBKB]] [[param-EXTENSION_ZBKB]]
===== EXTENSION_ZBKB ===== EXTENSION_ZBKB
@ -103,7 +103,7 @@ Support for Zbkb basic bit manipulation for cryptography.
Requires: <<param-EXTENSION_ZBB>>. (Since Zbb and Zbkb have a large overlap, this flag enables only those instructions which are in Zbkb but aren't in Zbb. Therefore both flags must be set for full Zbkb support.) Requires: <<param-EXTENSION_ZBB>>. (Since Zbb and Zbkb have a large overlap, this flag enables only those instructions which are in Zbkb but aren't in Zbb. Therefore both flags must be set for full Zbkb support.)
Default value: 1 Default value: 0
[[param-EXTENSION_ZIFENCEI]] [[param-EXTENSION_ZIFENCEI]]
===== EXTENSION_ZIFENCEI ===== EXTENSION_ZIFENCEI
@ -113,17 +113,17 @@ this instruction is optional, since a plain branch/jump is sufficient to
flush the instruction prefetch queue. When the branch predictor is enabled flush the instruction prefetch queue. When the branch predictor is enabled
(<<param-BRANCH_PREDICTOR>> is 1), this instruction must be implemented. (<<param-BRANCH_PREDICTOR>> is 1), this instruction must be implemented.
Default value: 1 Default value: 0
[[cfg-custom-extensions]]
==== Custom Hazard3 Extensions
[[param-EXTENSION_XH3BEXTM]] [[param-EXTENSION_XH3BEXTM]]
===== EXTENSION_XH3BEXTM ===== EXTENSION_XH3BEXTM
Custom bit manipulation instructions for Hazard3: `h3.bextm` and `h3.bextmi`. See <<extension-xh3bextm-section>>. Custom bit manipulation instructions for Hazard3: `h3.bextm` and `h3.bextmi`. See <<extension-xh3bextm-section>>.
Default value: 1 Default value: 0
[[cfg-custom-extensions]]
==== Custom Hazard3 Extensions
[[param-EXTENSION_XH3IRQ]] [[param-EXTENSION_XH3IRQ]]
===== EXTENSION_XH3IRQ ===== EXTENSION_XH3IRQ
@ -132,21 +132,21 @@ Custom preemptive, prioritised interrupt support. Can be disabled if an
external interrupt controller (e.g. PLIC) is used. If disabled, and external interrupt controller (e.g. PLIC) is used. If disabled, and
NUM_IRQS > 1, the external interrupts are simply OR'd into mip.meip. See <<extension-xh3irq-section>>. NUM_IRQS > 1, the external interrupts are simply OR'd into mip.meip. See <<extension-xh3irq-section>>.
Default value: 1 Default value: 0
[[param-EXTENSION_XH3PMPM]] [[param-EXTENSION_XH3PMPM]]
===== EXTENSION_XH3PMPM ===== EXTENSION_XH3PMPM
Custom PMPCFGMx CSRs to enforce PMP regions in M-mode without locking. See <<extension-xh3pmpm-section>>. Custom PMPCFGMx CSRs to enforce PMP regions in M-mode without locking. See <<extension-xh3pmpm-section>>.
Default value: 0
[[param-EXTENSION_XH3POWER]] [[param-EXTENSION_XH3POWER]]
===== EXTENSION_XH3POWER ===== EXTENSION_XH3POWER
Custom power management controls for Hazard3. This adds the <<reg-msleep>> CSR, and the `h3.block` and `h3.unblock` hint instructions. See <<extension-xh3power-section>> Custom power management controls for Hazard3. This adds the <<reg-msleep>> CSR, and the `h3.block` and `h3.unblock` hint instructions. See <<extension-xh3power-section>>
Default value: 1 Default value: 0
==== CSR support ==== CSR support
@ -162,16 +162,22 @@ the privileged specification itself is an optional extension. Hazard3 allows
the mandatory CSRs to be disabled to save a small amount of area in the mandatory CSRs to be disabled to save a small amount of area in
deeply-embedded implementations. deeply-embedded implementations.
Default value: 1
[[param-CSR_M_TRAP]] [[param-CSR_M_TRAP]]
===== CSR_M_TRAP ===== CSR_M_TRAP
Include M-mode trap-handling CSRs, and enable trap support. Include M-mode trap-handling CSRs, and enable trap support.
Default value: 1
[[param-CSR_COUNTER]] [[param-CSR_COUNTER]]
===== CSR_COUNTER ===== CSR_COUNTER
Include the basic performance counters (`cycle`/`instret`) and relevant CSRs. Note that these performance counters are now in their own separate extension (Zicntr) and are no longer mandatory. Include the basic performance counters (`cycle`/`instret`) and relevant CSRs. Note that these performance counters are now in their own separate extension (Zicntr) and are no longer mandatory.
Default value: 0
[[param-U_MODE]] [[param-U_MODE]]
===== U_MODE ===== U_MODE
@ -182,22 +188,26 @@ memory.
Requires: <<param-CSR_M_TRAP>>. Requires: <<param-CSR_M_TRAP>>.
Default value: 0
[[param-PMP_REGIONS]] [[param-PMP_REGIONS]]
===== PMP_REGIONS ===== PMP_REGIONS
Number of physical memory protection regions, or 0 for no PMP. PMP is more Number of physical memory protection regions, or 0 for no PMP. PMP is more
useful if U mode is supported, but this is not a requirement. useful if U-mode is supported, but this is not a requirement.
Hazard3's PMP supports only the NAPOT and(if <<param-PMP_GRAIN>> is 0) NA4 Hazard3's PMP supports only the NAPOT and(if <<param-PMP_GRAIN>> is 0) NA4
region types. region types.
Requires: <<param-CSR_M_TRAP>>. Requires: <<param-CSR_M_TRAP>>.
Default value: 0
[[param-PMP_GRAIN]] [[param-PMP_GRAIN]]
===== PMP_GRAIN ===== PMP_GRAIN
This is the _G_ parameter in the privileged spec, which defines the This is the _G_ parameter in the privileged spec, which defines the
granularity of PMP regions. Minimum PMP region size is 1 <<(_G_ + 2) bytes. granularity of PMP regions. Minimum PMP region size is 1 << (_G_ + 2) bytes.
If _G_ > 0, `pmcfg.a` can not be set to NA4 (attempting to do so will set the If _G_ > 0, `pmcfg.a` can not be set to NA4 (attempting to do so will set the
region to OFF instead). region to OFF instead).
@ -266,18 +276,19 @@ Default value: 0
[[param-NUM_IRQS]] [[param-NUM_IRQS]]
===== NUM_IRQS ===== NUM_IRQS
Number of external IRQs implemented in meiea, meipa, meifa and meipra, if NUM_IRQS: Number of external IRQs. Minimum 1, maximum 512. Note that if
<<param-CSR_M_TRAP>> is enabled. Minimum 1, maximum 512. <<param-EXTENSION_XH3IRQ>> (Hazard3 interrupt controller) is disabled then
multiple external interrupts are simply OR'd into mip.meip.
Default value: 32 Default value: 1
[[param-IRQ_PRIORITY_BITS]] [[param-IRQ_PRIORITY_BITS]]
===== IRQ_PRIORITY_BITS ===== IRQ_PRIORITY_BITS
Number of priority bits implemented for each interrupt in meipra. The IRQ_PRIORITY_BITS: Number of priority bits implemented for each interrupt
number of distinct levels is (1 << IRQ_PRIORITY_BITS). Minimum 0, max 4. in meipra, if EXTENSION_XH3IRQ is enabled. The number of distinct levels
Note that having more than 1 priority level with a large number of IRQs is (1 << IRQ_PRIORITY_BITS). Minimum 0, max 4. Note that multiple priority
will have a severe effect on timing. levels with a large number of IRQs will have a severe effect on timing.
Default value: 0 Default value: 0
@ -285,7 +296,9 @@ Default value: 0
===== IRQ_INPUT_BYPASS ===== IRQ_INPUT_BYPASS
Disable the input registers on the external interrupts, to reduce latency by Disable the input registers on the external interrupts, to reduce latency by
one cycle. Can be done on an IRQ-by-IRQ basis. one cycle. Can be applied on an IRQ-by-IRQ basis.
Ignored if <<param-EXTENSION_XH3IRQ>> is disabled.
Default value: all-zeroes (not bypassed). Default value: all-zeroes (not bypassed).
@ -397,7 +410,7 @@ nontaken branch, a fence.i or a trap. Successful prediction eliminates the
Requires: <<param-EXTENSION_ZIFENCEI>> Requires: <<param-EXTENSION_ZIFENCEI>>
Default value: 1 Default value: 0
[[param-MTVEC_WMASK]] [[param-MTVEC_WMASK]]
===== MTVEC_WMASK ===== MTVEC_WMASK

43
hdl/hazard3_config.vh
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@ -43,43 +43,43 @@ parameter EXTENSION_C = 1,
parameter EXTENSION_M = 1, parameter EXTENSION_M = 1,
// EXTENSION_ZBA: Support for Zba address generation instructions // EXTENSION_ZBA: Support for Zba address generation instructions
parameter EXTENSION_ZBA = 1, parameter EXTENSION_ZBA = 0,
// EXTENSION_ZBB: Support for Zbb basic bit manipulation instructions // EXTENSION_ZBB: Support for Zbb basic bit manipulation instructions
parameter EXTENSION_ZBB = 1, parameter EXTENSION_ZBB = 0,
// EXTENSION_ZBC: Support for Zbc carry-less multiplication instructions // EXTENSION_ZBC: Support for Zbc carry-less multiplication instructions
parameter EXTENSION_ZBC = 1, parameter EXTENSION_ZBC = 0,
// EXTENSION_ZBS: Support for Zbs single-bit manipulation instructions // EXTENSION_ZBS: Support for Zbs single-bit manipulation instructions
parameter EXTENSION_ZBS = 1, parameter EXTENSION_ZBS = 0,
// EXTENSION_ZBKB: Support for Zbkb basic bit manipulation for cryptography // EXTENSION_ZBKB: Support for Zbkb basic bit manipulation for cryptography
// Requires: Zbb. (This flag enables instructions in Zbkb which aren't in Zbb.) // Requires: Zbb. (This flag enables instructions in Zbkb which aren't in Zbb.)
parameter EXTENSION_ZBKB = 1, parameter EXTENSION_ZBKB = 0,
// EXTENSION_ZIFENCEI: Support for the fence.i instruction // EXTENSION_ZIFENCEI: Support for the fence.i instruction
// Optional, since a plain branch/jump will also flush the prefetch queue. // Optional, since a plain branch/jump will also flush the prefetch queue.
parameter EXTENSION_ZIFENCEI = 1, parameter EXTENSION_ZIFENCEI = 0,
// ---------------------------------------------------------------------------- // ----------------------------------------------------------------------------
// Custom RISC-V extensions // Custom RISC-V extensions
// EXTENSION_XH3B: Custom bit-extract-multiple instructions for Hazard3 // EXTENSION_XH3B: Custom bit-extract-multiple instructions for Hazard3
parameter EXTENSION_XH3BEXTM = 1, parameter EXTENSION_XH3BEXTM = 0,
// EXTENSION_XH3IRQ: Custom preemptive, prioritised interrupt support. Can be // EXTENSION_XH3IRQ: Custom preemptive, prioritised interrupt support. Can be
// disabled if an external interrupt controller (e.g. PLIC) is used. If // disabled if an external interrupt controller (e.g. PLIC) is used. If
// disabled, and NUM_IRQS > 1, the external interrupts are simply OR'd into // disabled, and NUM_IRQS > 1, the external interrupts are simply OR'd into
// mip.meip. // mip.meip.
parameter EXTENSION_XH3IRQ = 1, parameter EXTENSION_XH3IRQ = 0,
// EXTENSION_XH3PMPM: PMPCFGMx CSRs to enforce PMP regions in M-mode without // EXTENSION_XH3PMPM: PMPCFGMx CSRs to enforce PMP regions in M-mode without
// locking. Unlike ePMP mseccfg.rlb, locked and unlocked regions can coexist // locking. Unlike ePMP mseccfg.rlb, locked and unlocked regions can coexist
parameter EXTENSION_XH3PMPM = 1, parameter EXTENSION_XH3PMPM = 0,
// EXTENSION_XH3POWER: Custom power management controls for Hazard3 // EXTENSION_XH3POWER: Custom power management controls for Hazard3
parameter EXTENSION_XH3POWER = 1, parameter EXTENSION_XH3POWER = 0,
// ---------------------------------------------------------------------------- // ----------------------------------------------------------------------------
// Standard CSR support // Standard CSR support
@ -94,8 +94,8 @@ parameter CSR_M_MANDATORY = 1,
// CSR_M_TRAP: Include M-mode trap-handling CSRs, and enable trap support. // CSR_M_TRAP: Include M-mode trap-handling CSRs, and enable trap support.
parameter CSR_M_TRAP = 1, parameter CSR_M_TRAP = 1,
// CSR_COUNTER: Include performance counters and relevant M-mode CSRs // CSR_COUNTER: Include performance counters and Zicntr CSRs
parameter CSR_COUNTER = 1, parameter CSR_COUNTER = 0,
// U_MODE: Support the U (user) execution mode. In U mode, the core performs // U_MODE: Support the U (user) execution mode. In U mode, the core performs
// unprivileged bus accesses, and software's access to CSRs is restricted. // unprivileged bus accesses, and software's access to CSRs is restricted.
@ -140,19 +140,20 @@ parameter BREAKPOINT_TRIGGERS = 0,
// ---------------------------------------------------------------------------- // ----------------------------------------------------------------------------
// External interrupt support // External interrupt support
// NUM_IRQS: Number of external IRQs implemented in meiea, meipa, meifa and // NUM_IRQS: Number of external IRQs. Minimum 1, maximum 512. Note that if
// meipra, if CSR_M_TRAP is enabled. Minimum 1, maximum 512. // EXTENSION_XH3IRQ (Hazard3 interrupt controller) is disabled then multiple
parameter NUM_IRQS = 32, // external interrupts are simply OR'd into mip.meip.
parameter NUM_IRQS = 1,
// IRQ_PRIORITY_BITS: Number of priority bits implemented for each interrupt // IRQ_PRIORITY_BITS: Number of priority bits implemented for each interrupt
// in meipra. The number of distinct levels is (1 << IRQ_PRIORITY_BITS). // in meipra, if EXTENSION_XH3IRQ is enabled. The number of distinct levels
// Minimum 0, max 4. Note that having more than 1 priority level with a large // is (1 << IRQ_PRIORITY_BITS). Minimum 0, max 4. Note that multiple priority
// number of IRQs will have a severe effect on timing. Ignored if // levels with a large number of IRQs will have a severe effect on timing.
// EXTENSION_XH3IRQ is disabled.
parameter IRQ_PRIORITY_BITS = 0, parameter IRQ_PRIORITY_BITS = 0,
// IRQ_INPUT_BYPASS: disable the input registers on the external interrupts, // IRQ_INPUT_BYPASS: disable the input registers on the external interrupts,
// to reduce latency by one cycle. Can be done on an IRQ-by-IRQ basis. // to reduce latency by one cycle. Can be applied on an IRQ-by-IRQ basis.
// Ignored if EXTENSION_XH3IRQ is disabled.
parameter IRQ_INPUT_BYPASS = {NUM_IRQS{1'b0}}, parameter IRQ_INPUT_BYPASS = {NUM_IRQS{1'b0}},
// ---------------------------------------------------------------------------- // ----------------------------------------------------------------------------
@ -213,7 +214,7 @@ parameter RESET_REGFILE = 1,
// cleared on a mispredicted nontaken branch, a fence.i or a trap. Successful // cleared on a mispredicted nontaken branch, a fence.i or a trap. Successful
// prediction eliminates the 1-cyle fetch bubble on a taken branch, usually // prediction eliminates the 1-cyle fetch bubble on a taken branch, usually
// making tight loops faster. // making tight loops faster.
parameter BRANCH_PREDICTOR = 1, parameter BRANCH_PREDICTOR = 0,
// MTVEC_WMASK: Mask of which bits in mtvec are writable. Full writability is // MTVEC_WMASK: Mask of which bits in mtvec are writable. Full writability is
// recommended, because a common idiom in setup code is to set mtvec just // recommended, because a common idiom in setup code is to set mtvec just