Revise default config values, and update docs with new values
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Luke Wren
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8220
doc/hazard3.pdf
8220
doc/hazard3.pdf
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@ -73,28 +73,28 @@ Default value: 1
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Support for Zba address generation instructions. 0 for disable, 1 for enable.
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Default value: 1
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Default value: 0
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[[param-EXTENSION_ZBB]]
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===== EXTENSION_ZBB
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Support for Zbb basic bit manipulation instructions. 0 for disable, 1 for enable.
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Default value: 1
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Default value: 0
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[[param-EXTENSION_ZBC]]
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===== EXTENSION_ZBC
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Support for Zbc carry-less multiplication instructions. 0 for disable, 1 for enable.
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Default value: 1
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Default value: 0
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[[param-EXTENSION_ZBS]]
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===== EXTENSION_ZBS
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Support for Zbs single-bit manipulation instructions. 0 for disable, 1 for enable.
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Default value: 1
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Default value: 0
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[[param-EXTENSION_ZBKB]]
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===== EXTENSION_ZBKB
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@ -103,7 +103,7 @@ Support for Zbkb basic bit manipulation for cryptography.
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Requires: <<param-EXTENSION_ZBB>>. (Since Zbb and Zbkb have a large overlap, this flag enables only those instructions which are in Zbkb but aren't in Zbb. Therefore both flags must be set for full Zbkb support.)
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Default value: 1
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Default value: 0
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[[param-EXTENSION_ZIFENCEI]]
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===== EXTENSION_ZIFENCEI
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@ -113,17 +113,17 @@ this instruction is optional, since a plain branch/jump is sufficient to
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flush the instruction prefetch queue. When the branch predictor is enabled
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(<<param-BRANCH_PREDICTOR>> is 1), this instruction must be implemented.
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Default value: 1
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Default value: 0
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[[cfg-custom-extensions]]
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==== Custom Hazard3 Extensions
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[[param-EXTENSION_XH3BEXTM]]
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===== EXTENSION_XH3BEXTM
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Custom bit manipulation instructions for Hazard3: `h3.bextm` and `h3.bextmi`. See <<extension-xh3bextm-section>>.
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Default value: 1
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[[cfg-custom-extensions]]
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==== Custom Hazard3 Extensions
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Default value: 0
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[[param-EXTENSION_XH3IRQ]]
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===== EXTENSION_XH3IRQ
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@ -132,21 +132,21 @@ Custom preemptive, prioritised interrupt support. Can be disabled if an
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external interrupt controller (e.g. PLIC) is used. If disabled, and
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NUM_IRQS > 1, the external interrupts are simply OR'd into mip.meip. See <<extension-xh3irq-section>>.
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Default value: 1
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Default value: 0
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[[param-EXTENSION_XH3PMPM]]
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===== EXTENSION_XH3PMPM
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Custom PMPCFGMx CSRs to enforce PMP regions in M-mode without locking. See <<extension-xh3pmpm-section>>.
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Default value: 0
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[[param-EXTENSION_XH3POWER]]
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===== EXTENSION_XH3POWER
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Custom power management controls for Hazard3. This adds the <<reg-msleep>> CSR, and the `h3.block` and `h3.unblock` hint instructions. See <<extension-xh3power-section>>
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Default value: 1
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Default value: 0
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==== CSR support
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@ -162,16 +162,22 @@ the privileged specification itself is an optional extension. Hazard3 allows
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the mandatory CSRs to be disabled to save a small amount of area in
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deeply-embedded implementations.
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Default value: 1
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[[param-CSR_M_TRAP]]
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===== CSR_M_TRAP
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Include M-mode trap-handling CSRs, and enable trap support.
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Default value: 1
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[[param-CSR_COUNTER]]
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===== CSR_COUNTER
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Include the basic performance counters (`cycle`/`instret`) and relevant CSRs. Note that these performance counters are now in their own separate extension (Zicntr) and are no longer mandatory.
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Default value: 0
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[[param-U_MODE]]
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===== U_MODE
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@ -182,22 +188,26 @@ memory.
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Requires: <<param-CSR_M_TRAP>>.
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Default value: 0
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[[param-PMP_REGIONS]]
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===== PMP_REGIONS
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Number of physical memory protection regions, or 0 for no PMP. PMP is more
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useful if U mode is supported, but this is not a requirement.
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useful if U-mode is supported, but this is not a requirement.
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Hazard3's PMP supports only the NAPOT and(if <<param-PMP_GRAIN>> is 0) NA4
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region types.
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Requires: <<param-CSR_M_TRAP>>.
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Default value: 0
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[[param-PMP_GRAIN]]
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===== PMP_GRAIN
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This is the _G_ parameter in the privileged spec, which defines the
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granularity of PMP regions. Minimum PMP region size is 1 <<(_G_ + 2) bytes.
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granularity of PMP regions. Minimum PMP region size is 1 << (_G_ + 2) bytes.
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If _G_ > 0, `pmcfg.a` can not be set to NA4 (attempting to do so will set the
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region to OFF instead).
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@ -266,18 +276,19 @@ Default value: 0
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[[param-NUM_IRQS]]
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===== NUM_IRQS
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Number of external IRQs implemented in meiea, meipa, meifa and meipra, if
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<<param-CSR_M_TRAP>> is enabled. Minimum 1, maximum 512.
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NUM_IRQS: Number of external IRQs. Minimum 1, maximum 512. Note that if
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<<param-EXTENSION_XH3IRQ>> (Hazard3 interrupt controller) is disabled then
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multiple external interrupts are simply OR'd into mip.meip.
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Default value: 32
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Default value: 1
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[[param-IRQ_PRIORITY_BITS]]
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===== IRQ_PRIORITY_BITS
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Number of priority bits implemented for each interrupt in meipra. The
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number of distinct levels is (1 << IRQ_PRIORITY_BITS). Minimum 0, max 4.
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Note that having more than 1 priority level with a large number of IRQs
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will have a severe effect on timing.
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IRQ_PRIORITY_BITS: Number of priority bits implemented for each interrupt
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in meipra, if EXTENSION_XH3IRQ is enabled. The number of distinct levels
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is (1 << IRQ_PRIORITY_BITS). Minimum 0, max 4. Note that multiple priority
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levels with a large number of IRQs will have a severe effect on timing.
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Default value: 0
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@ -285,7 +296,9 @@ Default value: 0
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===== IRQ_INPUT_BYPASS
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Disable the input registers on the external interrupts, to reduce latency by
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one cycle. Can be done on an IRQ-by-IRQ basis.
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one cycle. Can be applied on an IRQ-by-IRQ basis.
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Ignored if <<param-EXTENSION_XH3IRQ>> is disabled.
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Default value: all-zeroes (not bypassed).
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@ -397,7 +410,7 @@ nontaken branch, a fence.i or a trap. Successful prediction eliminates the
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Requires: <<param-EXTENSION_ZIFENCEI>>
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Default value: 1
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Default value: 0
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[[param-MTVEC_WMASK]]
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===== MTVEC_WMASK
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@ -43,43 +43,43 @@ parameter EXTENSION_C = 1,
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parameter EXTENSION_M = 1,
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// EXTENSION_ZBA: Support for Zba address generation instructions
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parameter EXTENSION_ZBA = 1,
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parameter EXTENSION_ZBA = 0,
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// EXTENSION_ZBB: Support for Zbb basic bit manipulation instructions
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parameter EXTENSION_ZBB = 1,
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parameter EXTENSION_ZBB = 0,
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// EXTENSION_ZBC: Support for Zbc carry-less multiplication instructions
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parameter EXTENSION_ZBC = 1,
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parameter EXTENSION_ZBC = 0,
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// EXTENSION_ZBS: Support for Zbs single-bit manipulation instructions
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parameter EXTENSION_ZBS = 1,
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parameter EXTENSION_ZBS = 0,
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// EXTENSION_ZBKB: Support for Zbkb basic bit manipulation for cryptography
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// Requires: Zbb. (This flag enables instructions in Zbkb which aren't in Zbb.)
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parameter EXTENSION_ZBKB = 1,
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parameter EXTENSION_ZBKB = 0,
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// EXTENSION_ZIFENCEI: Support for the fence.i instruction
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// Optional, since a plain branch/jump will also flush the prefetch queue.
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parameter EXTENSION_ZIFENCEI = 1,
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parameter EXTENSION_ZIFENCEI = 0,
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// ----------------------------------------------------------------------------
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// Custom RISC-V extensions
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// EXTENSION_XH3B: Custom bit-extract-multiple instructions for Hazard3
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parameter EXTENSION_XH3BEXTM = 1,
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parameter EXTENSION_XH3BEXTM = 0,
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// EXTENSION_XH3IRQ: Custom preemptive, prioritised interrupt support. Can be
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// disabled if an external interrupt controller (e.g. PLIC) is used. If
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// disabled, and NUM_IRQS > 1, the external interrupts are simply OR'd into
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// mip.meip.
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parameter EXTENSION_XH3IRQ = 1,
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parameter EXTENSION_XH3IRQ = 0,
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// EXTENSION_XH3PMPM: PMPCFGMx CSRs to enforce PMP regions in M-mode without
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// locking. Unlike ePMP mseccfg.rlb, locked and unlocked regions can coexist
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parameter EXTENSION_XH3PMPM = 1,
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parameter EXTENSION_XH3PMPM = 0,
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// EXTENSION_XH3POWER: Custom power management controls for Hazard3
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parameter EXTENSION_XH3POWER = 1,
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parameter EXTENSION_XH3POWER = 0,
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// ----------------------------------------------------------------------------
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// Standard CSR support
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@ -94,8 +94,8 @@ parameter CSR_M_MANDATORY = 1,
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// CSR_M_TRAP: Include M-mode trap-handling CSRs, and enable trap support.
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parameter CSR_M_TRAP = 1,
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// CSR_COUNTER: Include performance counters and relevant M-mode CSRs
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parameter CSR_COUNTER = 1,
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// CSR_COUNTER: Include performance counters and Zicntr CSRs
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parameter CSR_COUNTER = 0,
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// U_MODE: Support the U (user) execution mode. In U mode, the core performs
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// unprivileged bus accesses, and software's access to CSRs is restricted.
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@ -140,19 +140,20 @@ parameter BREAKPOINT_TRIGGERS = 0,
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// ----------------------------------------------------------------------------
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// External interrupt support
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// NUM_IRQS: Number of external IRQs implemented in meiea, meipa, meifa and
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// meipra, if CSR_M_TRAP is enabled. Minimum 1, maximum 512.
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parameter NUM_IRQS = 32,
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// NUM_IRQS: Number of external IRQs. Minimum 1, maximum 512. Note that if
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// EXTENSION_XH3IRQ (Hazard3 interrupt controller) is disabled then multiple
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// external interrupts are simply OR'd into mip.meip.
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parameter NUM_IRQS = 1,
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// IRQ_PRIORITY_BITS: Number of priority bits implemented for each interrupt
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// in meipra. The number of distinct levels is (1 << IRQ_PRIORITY_BITS).
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// Minimum 0, max 4. Note that having more than 1 priority level with a large
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// number of IRQs will have a severe effect on timing. Ignored if
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// EXTENSION_XH3IRQ is disabled.
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// in meipra, if EXTENSION_XH3IRQ is enabled. The number of distinct levels
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// is (1 << IRQ_PRIORITY_BITS). Minimum 0, max 4. Note that multiple priority
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// levels with a large number of IRQs will have a severe effect on timing.
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parameter IRQ_PRIORITY_BITS = 0,
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// IRQ_INPUT_BYPASS: disable the input registers on the external interrupts,
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// to reduce latency by one cycle. Can be done on an IRQ-by-IRQ basis.
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// to reduce latency by one cycle. Can be applied on an IRQ-by-IRQ basis.
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// Ignored if EXTENSION_XH3IRQ is disabled.
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parameter IRQ_INPUT_BYPASS = {NUM_IRQS{1'b0}},
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// ----------------------------------------------------------------------------
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@ -213,7 +214,7 @@ parameter RESET_REGFILE = 1,
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// cleared on a mispredicted nontaken branch, a fence.i or a trap. Successful
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// prediction eliminates the 1-cyle fetch bubble on a taken branch, usually
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// making tight loops faster.
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parameter BRANCH_PREDICTOR = 1,
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parameter BRANCH_PREDICTOR = 0,
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// MTVEC_WMASK: Mask of which bits in mtvec are writable. Full writability is
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// recommended, because a common idiom in setup code is to set mtvec just
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