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Fix wrong reg readaddr when D starvation ends during a downstream load/store dphase stall (was using garbage from D instead of new fetch data predecoded in F)

This commit is contained in:
Luke Wren 2021-05-29 19:32:12 +01:00
parent f23ec3f941
commit 4b9a3c2c78
2 changed files with 6 additions and 3 deletions
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6
hdl/hazard3_core.v
View File

@ -140,6 +140,7 @@ end
//synthesis translate_on
// To X
wire d_starved;
wire [W_DATA-1:0] d_imm;
wire [W_REGADDR-1:0] d_rs1;
wire [W_REGADDR-1:0] d_rs2;
@ -174,6 +175,7 @@ hazard3_decode #(
.d_pc (d_pc),
.x_jump_not_except (x_jump_not_except),
.d_starved (d_starved),
.d_stall (d_stall),
.x_stall (x_stall),
.f_jump_rdy (f_jump_rdy),
@ -674,9 +676,9 @@ hazard3_regfile_1w2r #(
.rst_n (rst_n),
// On downstream stall, we feed D's addresses back into regfile
// so that output does not change.
.raddr1 (x_stall ? d_rs1 : f_rs1),
.raddr1 (x_stall && !d_starved ? d_rs1 : f_rs1),
.rdata1 (x_rdata1),
.raddr2 (x_stall ? d_rs2 : f_rs2),
.raddr2 (x_stall && !d_starved ? d_rs2 : f_rs2),
.rdata2 (x_rdata2),
.waddr (xm_rd),

3
hdl/hazard3_decode.v
View File

@ -31,6 +31,7 @@ module hazard3_decode #(
output wire df_cir_lock,
output wire [W_ADDR-1:0] d_pc,
output wire d_starved,
output wire d_stall,
input wire x_stall,
input wire f_jump_rdy,
@ -91,7 +92,7 @@ wire [31:0] d_imm_j = {{12{d_instr[31]}}, d_instr[19:12], d_instr[20], d_instr[3
// ----------------------------------------------------------------------------
// PC/CIR control
wire d_starved = ~|fd_cir_vld || fd_cir_vld[0] && d_instr_is_32bit;
assign d_starved = ~|fd_cir_vld || fd_cir_vld[0] && d_instr_is_32bit;
assign d_stall = x_stall || d_starved;
assign df_cir_use =