Add OrangeCrab 25F support (#7)
* Add OrangeCrab 25F support * Fix whitespace Co-authored-by: Luke Wren <wren6991@gmail.com>
This commit is contained in:
Scott Shawcroft
GitHub
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file fpga_orangecrab_25f.v
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file ../libfpga/common/reset_sync.v
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file ../libfpga/common/fpga_reset.v
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list ../soc/soc.f
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# ECP5 DTM is not in main SoC list because the JTAGG primitive doesn't exist
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# on most platforms
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list ../../hdl/debug/dtm/hazard3_ecp5_jtag_dtm.f
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/*****************************************************************************\
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| Copyright (C) 2021 Luke Wren |
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| SPDX-License-Identifier: Apache-2.0 |
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\*****************************************************************************/
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`default_nettype none
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module fpga_orangecrab_25f (
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input wire clk_osc,
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output wire [7:0] dbg,
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output wire uart_tx,
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input wire uart_rx,
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output rgb_led0_r,
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output rgb_led0_g,
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output rgb_led0_b,
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output rst_n,
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input usr_btn
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);
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wire clk_sys = clk_osc;
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wire rst_n_sys;
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wire trst_n;
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fpga_reset #(
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.SHIFT (3)
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) rstgen (
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.clk (clk_sys),
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.force_rst_n (1'b1),
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.rst_n (rst_n_sys)
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);
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example_soc #(
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.DTM_TYPE ("ECP5"),
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.SRAM_DEPTH (1 << 14),
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.CLK_MHZ (48),
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.EXTENSION_M (1),
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.EXTENSION_A (1),
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.EXTENSION_C (0),
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.EXTENSION_ZBA (0),
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.EXTENSION_ZBB (0),
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.EXTENSION_ZBC (0),
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.EXTENSION_ZBS (0),
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.EXTENSION_ZBKB (0),
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.EXTENSION_ZIFENCEI (1),
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.EXTENSION_XH3BEXTM (0),
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.EXTENSION_XH3PMPM (0),
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.EXTENSION_XH3POWER (0),
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.CSR_COUNTER (1),
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.MUL_FAST (1),
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.MUL_FASTER (0),
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.MULH_FAST (0),
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.MULDIV_UNROLL (1),
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.FAST_BRANCHCMP (1),
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.BRANCH_PREDICTOR (1)
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) soc_u (
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.clk (clk_sys),
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.rst_n (rst_n_sys),
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// JTAG connections provided internally by ECP5 JTAGG primitive
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.tck (1'b0),
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.trst_n (1'b0),
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.tms (1'b0),
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.tdi (1'b0),
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.tdo (/* unused */),
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.uart_tx (uart_tx),
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.uart_rx (uart_rx)
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);
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// Create a 27 bit register
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reg [26:0] counter = 0;
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// Every positive edge increment register by 1
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always @(posedge clk_sys) begin
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counter <= counter + 1;
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end
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// Output inverted values of counter onto LEDs
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assign rgb_led0_r = ~counter[24];
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assign rgb_led0_g = ~counter[25];
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assign rgb_led0_b = 0;
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assign dbg = 8'hff;
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// Reset logic on button press.
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// this will enter the bootloader
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reg reset_sr = 1'b1;
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always @(posedge clk_sys) begin
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reset_sr <= {usr_btn};
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end
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assign rst_n = reset_sr;
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endmodule
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# Reference: https://github.com/emard/ulx3s/blob/master/doc/constraints/ulx3s_v20.lpf
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LOCATE COMP "clk_osc" SITE "A9";
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IOBUF PORT "clk_osc" PULLMODE=NONE IO_TYPE=LVCMOS33;
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FREQUENCY PORT "clk_osc" 48 MHZ;
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# UART TX/RX (from FPGA's point of view, i.e. TX is an output)
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LOCATE COMP "uart_tx" SITE "N17"; # FPGA transmits to ftdi
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LOCATE COMP "uart_rx" SITE "M18"; # FPGA receives from ftdi
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IOBUF PORT "uart_tx" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4;
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IOBUF PORT "uart_rx" PULLMODE=UP IO_TYPE=LVCMOS33;
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# 8 pins on an IO header for bringing signals out to a logic analyser
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LOCATE COMP "dbg[0]" SITE "H2"; # PCLK # "gn[0]"
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LOCATE COMP "dbg[1]" SITE "A8"; # PCLK # "gn[1]"
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LOCATE COMP "dbg[2]" SITE "B8"; # GR_PCLK # "gn[2]"
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LOCATE COMP "dbg[3]" SITE "C8"; # "gn[3]"
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LOCATE COMP "dbg[4]" SITE "B9"; # PCLK # "gp[0]"
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LOCATE COMP "dbg[5]" SITE "B10"; # PCLK # "gp[1]"
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LOCATE COMP "dbg[6]" SITE "L4"; # GR_PCLK # "gp[2]"
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LOCATE COMP "dbg[7]" SITE "N3"; # "gp[3]"
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IOBUF PORT "dbg[0]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4;
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IOBUF PORT "dbg[1]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4;
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IOBUF PORT "dbg[2]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4;
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IOBUF PORT "dbg[3]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4;
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IOBUF PORT "dbg[4]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4;
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IOBUF PORT "dbg[5]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4;
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IOBUF PORT "dbg[6]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4;
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IOBUF PORT "dbg[7]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4;
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LOCATE COMP "rgb_led0_r" SITE "K4";
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IOBUF PORT "rgb_led0_r" IO_TYPE=LVCMOS33;
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LOCATE COMP "rgb_led0_g" SITE "M3";
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IOBUF PORT "rgb_led0_g" IO_TYPE=LVCMOS33;
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LOCATE COMP "rgb_led0_b" SITE "J3";
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IOBUF PORT "rgb_led0_b" IO_TYPE=LVCMOS33;
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LOCATE COMP "usr_btn" SITE "J17";
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IOBUF PORT "usr_btn" IO_TYPE=SSTL135_I;
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LOCATE COMP "rst_n" SITE "V17";
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IOBUF PORT "rst_n" IO_TYPE=LVCMOS33;
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@ -0,0 +1,23 @@
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CHIPNAME=fpga_orangecrab_25f
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TOP=fpga_orangecrab_25f
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DOTF=../fpga/fpga_orangecrab_25f.f
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SYNTH_OPT=-abc9
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PNR_OPT=--timing-allow-fail
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DEVICE=25k
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PACKAGE=CSFBGA285
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DEVICE_IDCODE=0x41111043
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include $(SCRIPTS)/synth_ecp5.mk
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$(CHIPNAME).dfu: bit
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cp $(CHIPNAME).bit $@
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dfu-suffix -v 1209 -p 5af0 -a $@
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prog: bit
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ujprog $(CHIPNAME).bit
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flash: $(CHIPNAME).dfu
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dfu-util -d 1209:5af0 -D $<
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