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Maintain AMO IRQ holdoff when transitioning from data phase to error phase, to prevent error possibly being flushed

This commit is contained in:
Luke Wren 2021-12-06 19:27:20 +00:00
parent 29c5c8ca7f
commit 50d3d5d3b3
1 changed files with 6 additions and 1 deletions
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7
hdl/hazard3_core.v
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@ -606,8 +606,13 @@ always @ (posedge clk or negedge rst_n) begin
// taken once this load/store moves to the next stage: if another load/store
// is chasing down the pipeline then this is immediately suppressed by the
// IRQ entry, before its address phase can begin.
// Also hold off on AMOs, unless the AMO is transitioning to an address
// phase or completing. (This excludes transitions to error phase.)
xm_delay_irq_entry <= bus_aph_req_d && !bus_aph_ready_d ||
d_memop_is_amo && !((x_amo_phase == 3'h1 || x_amo_phase == 3'h3) && bus_dph_ready_d);
d_memop_is_amo && !((x_amo_phase == 3'h1 || x_amo_phase == 3'h3) && bus_dph_ready_d && !bus_dph_err_d);
if (!x_stall)
prev_instr_was_32_bit <= df_cir_use == 2'd2;
end