First pass at adding system bus access to DM. Currently only the 2-port processor supports SBA patchthrough.
This commit is contained in:
Luke Wren
parent
36cee73d1f
commit
51bc26f8ac
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@ -10,13 +10,16 @@
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module hazard3_dm #(
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// Where there are multiple harts per DM, the least-indexed hart is the
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// least-significant on each concatenated hart access bus.
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parameter N_HARTS = 1,
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parameter N_HARTS = 1,
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// Where there are multiple DMs, the address of each DM should be a
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// multiple of 'h200, so that bits[8:2] decode correctly.
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parameter NEXT_DM_ADDR = 32'h0000_0000,
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// Implement support for system bus access:
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parameter HAVE_SBA = 1,
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parameter XLEN = 32, // Do not modify
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parameter W_HARTSEL = N_HARTS > 1 ? $clog2(N_HARTS) : 1 // Do not modify
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// Do not modify:
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parameter XLEN = 32, // Do not modify
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parameter W_HARTSEL = N_HARTS > 1 ? $clog2(N_HARTS) : 1 // Do not modify
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) (
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// DM is assumed to be in same clock domain as core; clock crossing
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// (if any) is inside DTM, or between DTM and DM.
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@ -63,7 +66,21 @@ module hazard3_dm #(
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output wire [N_HARTS-1:0] hart_instr_data_vld,
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input wire [N_HARTS-1:0] hart_instr_data_rdy,
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input wire [N_HARTS-1:0] hart_instr_caught_exception,
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input wire [N_HARTS-1:0] hart_instr_caught_ebreak
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input wire [N_HARTS-1:0] hart_instr_caught_ebreak,
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// System bus access (optional) -- can be hooked up to the standalone AHB
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// shim (hazard3_sba_to_ahb.v) or the SBA input port on the processor
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// wrapper, which muxes SBA into the processor's load/store bus access
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// port. SBA does not increase debugger bus throughput, but supports
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// minimally intrusive debug bus access for e.g. Segger RTT.
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output wire [31:0] sbus_addr,
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output wire sbus_write,
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output wire [1:0] sbus_size,
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output wire sbus_vld,
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input wire sbus_rdy,
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input wire sbus_err,
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output wire [31:0] sbus_wdata,
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input wire [31:0] sbus_rdata
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);
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wire dmi_write = dmi_psel && dmi_penable && dmi_pready && dmi_pwrite;
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@ -100,7 +117,10 @@ localparam ADDR_CONFSTRPTR3 = 7'h1c;
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localparam ADDR_NEXTDM = 7'h1d;
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localparam ADDR_PROGBUF0 = 7'h20;
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localparam ADDR_PROGBUF1 = 7'h21;
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// No authentication, no system bus access
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// No authentication
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localparam ADDR_SBCS = 7'h38;
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localparam ADDR_SBADDRESS0 = 7'h39;
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localparam ADDR_SBDATA0 = 7'h3c;
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// APB is byte-addressed, DM registers are word-addressed.
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wire [6:0] dmi_regaddr = dmi_paddr[8:2];
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@ -289,6 +309,125 @@ end
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assign hart_req_resume = dmcontrol_resumereq_sticky;
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// ----------------------------------------------------------------------------
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// System bus access
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reg [31:0] sbaddress;
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reg [31:0] sbdata;
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// Update logic for address/data registers:
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reg sbbusy;
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reg sbautoincrement;
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reg [2:0] sbaccess; // Size of the transfer
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always @ (posedge clk or negedge rst_n) begin
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if (!rst_n) begin
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sbaddress <= {32{1'b0}};
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sbdata <= {32{1'b0}};
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end else if (!dmactive) begin
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sbaddress <= {32{1'b0}};
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sbdata <= {32{1'b0}};
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end else if (HAVE_SBA) begin
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if (dmi_write && dmi_regaddr == ADDR_SBDATA0 && !sbbusy) begin
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sbdata <= dmi_pwdata;
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end else if (sbus_vld && sbus_rdy && !sbus_write) begin
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sbdata <= sbus_rdata;
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end
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if (dmi_write && dmi_regaddr == ADDR_SBADDRESS0 && !sbbusy) begin
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sbaddress <= dmi_pwdata;
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end else if (sbus_vld && sbus_rdy && sbautoincrement) begin
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sbaddress <= sbaddress + (
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sbaccess[1:0] == 2'b00 ? 3'h1 :
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sbaccess[1:0] == 2'b01 ? 3'h2 : 3'h4
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);
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end
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end
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end
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// Control logic:
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reg sbbusyerror;
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reg sbreadonaddr;
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reg sbreadondata;
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reg [2:0] sberror;
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reg sb_current_is_write;
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localparam SBERROR_OK = 3'h0;
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localparam SBERROR_BADADDR = 3'h2;
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localparam SBERROR_BADALIGN = 3'h3;
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localparam SBERROR_BADSIZE = 3'h4;
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wire sb_want_start_write = dmi_write && dmi_regaddr == ADDR_SBDATA0;
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wire sb_want_start_read =
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(sbreadonaddr && dmi_write && dmi_regaddr == ADDR_SBADDRESS0) ||
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(sbreadondata && dmi_read && dmi_regaddr == ADDR_SBDATA0);
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wire sb_badalign =
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(sbaccess == 3'h1 && sbaddress[0]) ||
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(sbaccess == 3'h2 && |sbaddress[1:0]);
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wire sb_badsize = sbaccess > 3'h2;
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always @ (posedge clk or negedge rst_n) begin
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if (!rst_n) begin
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sbbusy <= 1'b0;
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sbbusyerror <= 1'b0;
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sbreadonaddr <= 1'b0;
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sbreadondata <= 1'b0;
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sbaccess <= 3'h0;
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sbautoincrement <= 1'b0;
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sberror <= 3'h0;
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sb_current_is_write <= 1'b0;
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end else if (!dmactive) begin
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sbbusy <= 1'b0;
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sbbusyerror <= 1'b0;
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sbreadonaddr <= 1'b0;
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sbreadondata <= 1'b0;
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sbaccess <= 3'h0;
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sbautoincrement <= 1'b0;
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sberror <= 3'h0;
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sb_current_is_write <= 1'b0;
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end else if (HAVE_SBA) begin
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if (dmi_write && dmi_regaddr == ADDR_SBCS) begin
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// Assume a transfer is not in progress when written (per spec)
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sbbusyerror <= sbbusyerror && !dmi_pwdata[22];
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sbreadonaddr <= dmi_pwdata[20];
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sbaccess <= dmi_pwdata[19:17];
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sbautoincrement <= dmi_pwdata[16];
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sbreadondata <= dmi_pwdata[15];
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sberror <= sberror & ~dmi_pwdata[14:12];
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end
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if (sbbusy) begin
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if (sb_want_start_read || sb_want_start_write) begin
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sbbusyerror <= 1'b1;
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end
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if (sbus_vld && sbus_rdy) begin
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sbbusy <= 1'b0;
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if (sbus_err) begin
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sberror <= SBERROR_BADADDR;
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end
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end
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end else if (sb_want_start_read || sb_want_start_write) begin
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if (sb_badsize) begin
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sberror <= SBERROR_BADSIZE;
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end else if (sb_badalign) begin
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sberror <= SBERROR_BADALIGN;
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end else begin
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sbbusy <= 1'b1;
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sb_current_is_write <= sb_want_start_write;
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end
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end
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end
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end
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assign sbus_addr = sbaddress;
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assign sbus_write = sb_current_is_write;
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assign sbus_size = sbaccess[1:0];
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assign sbus_vld = sbbusy;
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assign sbus_wdata = sbdata;
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// ----------------------------------------------------------------------------
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// Abstract command data registers
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@ -649,6 +788,21 @@ always @ (*) begin
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15'h0,
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abstractauto_autoexecdata // only data0 present
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};
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ADDR_SBCS: dmi_prdata = {
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3'h1, // version = 1
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6'h00,
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sbbusyerror,
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sbbusy,
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sbreadonaddr,
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sbaccess,
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sbautoincrement,
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sbreadondata,
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sberror,
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7'h20, // sbasize = 32
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5'b00111 // 8, 16, 32-bit transfers supported
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} & {32{|HAVE_SBA}};
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ADDR_SBDATA0: dmi_prdata = sbdata & {32{|HAVE_SBA}};
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ADDR_SBADDRESS0: dmi_prdata = sbaddress & {32{|HAVE_SBA}};
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ADDR_CONFSTRPTR0: dmi_prdata = 32'h4c296328;
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ADDR_CONFSTRPTR1: dmi_prdata = 32'h20656b75;
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ADDR_CONFSTRPTR2: dmi_prdata = 32'h6e657257;
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@ -64,6 +64,15 @@ module hazard3_cpu_2port #(
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output wire dbg_instr_data_rdy,
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output wire dbg_instr_caught_exception,
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output wire dbg_instr_caught_ebreak,
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// Optional debug system bus access patch-through
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input wire [31:0] dbg_sbus_addr,
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input wire dbg_sbus_write,
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input wire [1:0] dbg_sbus_size,
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input wire dbg_sbus_vld,
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output wire dbg_sbus_rdy,
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output wire dbg_sbus_err,
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input wire [31:0] dbg_sbus_wdata,
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output wire [31:0] dbg_sbus_rdata,
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// Level-sensitive interrupt sources
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input wire [NUM_IRQ-1:0] irq, // -> mip.meip
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@ -192,39 +201,78 @@ assign i_hprot = {
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// ----------------------------------------------------------------------------
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// Load/store port
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assign d_haddr = core_haddr_d;
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assign d_htrans = core_aph_req_d ? HTRANS_NSEQ : HTRANS_IDLE;
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assign d_hwrite = core_hwrite_d;
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assign d_hsize = core_hsize_d;
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assign d_hexcl = core_aph_excl_d;
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// The debug module has optional System Bus Access support, which can be muxed
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// into the processor's D port here (or connected to a standalone AHB shim).
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// This confers absolutely no advantage for debugger bus throughput, but
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// allows the debugger to access the bus with minimal disturbance to the
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// processor.
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reg dphase_active_d;
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always @ (posedge clk or negedge rst_n)
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if (!rst_n)
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dphase_active_d <= 1'b0;
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else if (d_hready)
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dphase_active_d <= core_aph_req_d;
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wire bus_gnt_d;
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wire bus_gnt_s;
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reg bus_hold_aph;
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reg [1:0] bus_gnt_ds_prev;
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reg bus_active_dph_d;
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reg bus_active_dph_s;
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always @ (posedge clk or negedge rst_n) begin
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if (!rst_n) begin
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bus_hold_aph <= 1'b0;
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bus_gnt_ds_prev <= 2'h0;
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end else begin
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bus_hold_aph <= d_htrans[1] && !d_hready && !d_hresp;
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bus_gnt_ds_prev <= {bus_gnt_d, bus_gnt_s};
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end
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end
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assign {bus_gnt_d, bus_gnt_s} =
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bus_hold_aph ? bus_gnt_ds_prev :
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core_aph_req_d ? 2'b10 :
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dbg_sbus_vld && !bus_active_dph_s ? 2'b01 :
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2'b00 ;
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always @ (posedge clk or negedge rst_n) begin
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if (!rst_n) begin
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bus_active_dph_d <= 1'b0;
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bus_active_dph_s <= 1'b0;
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end else if (d_hready) begin
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bus_active_dph_d <= bus_gnt_d;
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bus_active_dph_s <= bus_gnt_s;
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end
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end
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assign d_htrans = bus_gnt_d || bus_gnt_s ? HTRANS_NSEQ : HTRANS_IDLE;
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assign d_haddr = bus_gnt_s ? dbg_sbus_addr : core_haddr_d;
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assign d_hwrite = bus_gnt_s ? dbg_sbus_write : core_hwrite_d;
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assign d_hsize = bus_gnt_s ? dbg_sbus_size : core_hsize_d;
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assign d_hexcl = bus_gnt_s ? 1'b0 : core_aph_excl_d;
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assign d_hprot = {
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2'b00, // Noncacheable/nonbufferable
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bus_gnt_s || core_priv_d, // Privileged or Normal as per core state
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1'b1 // Data access
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};
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assign d_hwdata = bus_active_dph_s ? dbg_sbus_wdata : core_wdata_d;
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// D-side errors are reported even when not ready, so that the core can make
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// use of the two-phase error response to cleanly squash a second load/store
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// chasing the faulting one down the pipeline.
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assign core_aph_ready_d = d_hready && core_aph_req_d;
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assign core_dph_ready_d = d_hready && dphase_active_d;
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assign core_dph_err_d = dphase_active_d && d_hresp;
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assign core_dph_exokay_d = dphase_active_d && d_hexokay;
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assign core_aph_ready_d = d_hready && bus_gnt_d;
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assign core_dph_ready_d = bus_active_dph_d && d_hready;
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assign core_dph_err_d = bus_active_dph_d && d_hresp;
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assign core_dph_exokay_d = bus_active_dph_d && d_hexokay;
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assign core_rdata_d = d_hrdata;
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assign d_hwdata = core_wdata_d;
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assign dbg_sbus_err = bus_active_dph_s && d_hresp;
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assign dbg_sbus_rdy = bus_active_dph_s && d_hready;
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assign dbg_sbus_rdata = d_hrdata;
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assign d_hburst = 3'h0;
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assign d_hmastlock = 1'b0;
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assign d_hprot = {
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2'b00, // Noncacheable/nonbufferable
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core_priv_d, // Privileged or Normal as per core state
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1'b1 // Data access
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};
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endmodule
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`ifndef YOSYS
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`default_nettype wire
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`endif
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@ -124,6 +124,15 @@ wire [N_HARTS-1:0] hart_instr_data_rdy;
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wire [N_HARTS-1:0] hart_instr_caught_exception;
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wire [N_HARTS-1:0] hart_instr_caught_ebreak;
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wire [31:0] sbus_addr;
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wire sbus_write;
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wire [1:0] sbus_size;
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wire sbus_vld;
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wire sbus_rdy;
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wire sbus_err;
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wire [31:0] sbus_wdata;
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wire [31:0] sbus_rdata;
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hazard3_dm #(
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.N_HARTS (N_HARTS),
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.NEXT_DM_ADDR (0)
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@ -159,7 +168,16 @@ hazard3_dm #(
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.hart_instr_data_vld (hart_instr_data_vld),
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.hart_instr_data_rdy (hart_instr_data_rdy),
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.hart_instr_caught_exception (hart_instr_caught_exception),
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.hart_instr_caught_ebreak (hart_instr_caught_ebreak)
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.hart_instr_caught_ebreak (hart_instr_caught_ebreak),
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.sbus_addr (sbus_addr),
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.sbus_write (sbus_write),
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.sbus_size (sbus_size),
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.sbus_vld (sbus_vld),
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.sbus_rdy (sbus_rdy),
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.sbus_err (sbus_err),
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.sbus_wdata (sbus_wdata),
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.sbus_rdata (sbus_rdata)
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);
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@ -230,6 +248,15 @@ hazard3_cpu_2port #(
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.dbg_instr_caught_exception (hart_instr_caught_exception),
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.dbg_instr_caught_ebreak (hart_instr_caught_ebreak),
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.dbg_sbus_addr (sbus_addr),
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.dbg_sbus_write (sbus_write),
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.dbg_sbus_size (sbus_size),
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.dbg_sbus_vld (sbus_vld),
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.dbg_sbus_rdy (sbus_rdy),
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.dbg_sbus_err (sbus_err),
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.dbg_sbus_wdata (sbus_wdata),
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.dbg_sbus_rdata (sbus_rdata),
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.irq (irq),
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.soft_irq (soft_irq[0]),
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.timer_irq (timer_irq)
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