Remove useless midcr.eivect feature. Make mlei left-shift its value by 2.
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Luke Wren
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cd1b391714
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9865
doc/hazard3.pdf
9865
doc/hazard3.pdf
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@ -175,8 +175,6 @@ Trap vector base address. Read-write. Exactly which bits of `mtvec` can be modif
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NOTE: In the RISC-V specification, `mode` is a 2-bit write-any read-legal field in bits 1:0. Hazard3 implements this by hardwiring bit 1 to 0.
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NOTE: Hazard3 has an additional nonstandard vectoring mode, where external interrupts are each separated into distinct vectors and `mcause` values. This is enabled through the implementation-defined control register, <<reg-midcr>>, since the RISC-V specification reserves `mtvec.mode == 2, 3` for future standard use.
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==== mscratch
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Address: `0x340`
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@ -211,8 +209,6 @@ The most significant bit of `mcause` is set to 1 to indicate an interrupt cause,
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| 11 | External interrupt (`mip.meip`)
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|===
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Numbers >16 are used for to disambiguate between external IRQs when expanded vectoring is enabled -- see <<reg-midcr>>.
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The following exception causes may be set by Hazard3 hardware:
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[cols="10h,~", options="header"]
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@ -413,20 +409,6 @@ The Debug Module uses this mapping to exchange data with the core by injecting `
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This CSR address is given by the `dataaddress` field of the Debug Module's `hartinfo` register, and `hartinfo.dataaccess` is set to 0 to indicate this is a CSR mapping, not a memory mapping.
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[[reg-midcr]]
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==== midcr
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Address: `0xbc0`
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Implementation-defined control register. Miscellaneous nonstandard controls.
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[cols="10h,20h,~", options="header"]
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|===
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| Bits | Name | Description
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| 31:1 | - | RES0
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| 0 | `eivect` | Modified external interrupt vectoring. If 0, use standard behaviour: all external interrupts set interrupt `mcause` of 11 and vector to `mtvec + 0x2c`. If 1, external interrupts use distinct interrupt `mcause` numbers 16 upward, and distinct vectors `mtvec + (irq + 16) * 4`. Resets to 0. Has no effect when `mtvec[0]` is 0.
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|===
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[[reg-meie0]]
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==== meie0
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@ -464,24 +446,18 @@ When any bit is set in both `meip0` and `meie0`, the standard external interrupt
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In this case, the processor jumps to either:
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* `mtvec` directly, if vectoring is disabled (`mtvec[0]` is 0)
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* `mtvec + 0x2c`, if vectoring is enabled (`mtvec[0]` is 1) and modified external IRQ vectoring is disabled (`midcr.eivect` is 0)
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* `mtvect + (mlei + 16) * 4`, if vectoring is enabled (`mtvec[0]` is 1) and modified external IRQ vectoring is enabled (`midcr.eivect` is 1). `
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** `mlei` is a read-only CSR containing the lowest-numbered pending-and-enabled external interrupt.
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* `mtvec + 0x2c`, if vectoring is enabled (`mtvec[0]` is 1)
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==== mlei
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Address: `0xfe4`
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Lowest external interrupt. Contains the index of the lowest-numbered external interrupt which is both asserted in `meip0` and enabled in `meie0`. Can be used for faster software vectoring when modified external interrupt vectoring (`midcr.eivect = 1`) is not in use.
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Lowest external interrupt. Contains the index of the lowest-numbered external interrupt which is both asserted in `meip0` and enabled in `meie0`, left-shifted by 2 so that it can be used to index an array of 32-bit function pointers.
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[cols="10h,20h,~", options="header"]
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|===
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| Bits | Name | Description
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| 31:5 | - | RES0
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| 4:0 | - | Index of the lowest-numbered active external interrupt. A LSB-first priority encode of `meip0 & meie0`. Zero when no external interrupts are both pending and enabled.
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| 31:7 | - | RES0
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| 6:2 | - | Index of the lowest-numbered active external interrupt. A LSB-first priority encode of `meip0 & meie0`. Zero when no external interrupts are both pending and enabled.
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| 1:0 | - | RES0
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|===
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==== Maybe-adds
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An option to clear a bit in `meie0` when that interrupt is taken, and set it when an `mret` has a matching `mcause` for that interrupt. Makes preemption support easier.
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@ -244,7 +244,6 @@ localparam MHPMEVENT30 = 12'h33e; // WARL (we tie to 0)
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localparam MHPMEVENT31 = 12'h33f; // WARL (we tie to 0)
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// Custom M-mode CSRs:
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localparam MIDCR = 12'hbc0; // Implementation-defined control register (bag of bits)
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localparam MEIE0 = 12'hbe0; // External interrupt enable register 0
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localparam MEIP0 = 12'hfe0; // External interrupt pending register 0
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localparam MLEI = 12'hfe4; // Lowest external interrupt number
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@ -300,25 +299,6 @@ always @ (posedge clk or negedge rst_n) begin
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end
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end
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// ----------------------------------------------------------------------------
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// Implementation-defined control register
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localparam MIDCR_INIT = X0;
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localparam MIDCR_WMASK = 32'h00000001;
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reg [XLEN-1:0] midcr;
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always @ (posedge clk or negedge rst_n) begin
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if (!rst_n) begin
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midcr <= MIDCR_INIT;
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end else if (wen && addr == MIDCR) begin
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midcr <= update_nonconst(midcr, MIDCR_WMASK);
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end
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end
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// Modified external interrupt vectoring
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wire midcr_eivect = midcr[0];
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// ----------------------------------------------------------------------------
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// Trap-handling CSRs
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@ -872,11 +852,6 @@ always @ (*) begin
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// ------------------------------------------------------------------------
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// Custom CSRs
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MIDCR: if (CSR_M_TRAP) begin
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decode_match = 1'b1;
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rdata = midcr;
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end
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MEIE0: if (CSR_M_TRAP) begin
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decode_match = 1'b1;
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rdata = meie0;
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@ -889,7 +864,7 @@ always @ (*) begin
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MLEI: if (CSR_M_TRAP) begin
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decode_match = !wen_soon;
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rdata = {{XLEN-5{1'b0}}, mlei};
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rdata = {{XLEN-7{1'b0}}, mlei, 2'b00};
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end
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default: begin end
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@ -1023,11 +998,7 @@ assign mip = {
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3'h0 // Reserved
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};
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// When eivect = 1, mip.meip is masked from the standard IRQs, so that the
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// platform-specific causes and vectors are used instead.
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wire [31:0] mip_no_global = mip & ~(32'h800 & ~{XLEN{midcr_eivect}});
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wire standard_irq_active = |(mip_no_global & mie) && mstatus_mie && !dcsr_step;
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wire external_irq_active = external_irq_pending && mstatus_mie && !dcsr_step && mie_meie;
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wire irq_active = |(mip & mie) && mstatus_mie && !dcsr_step;
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// WFI clear respects individual interrupt enables but ignores mstatus.mie.
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// Additionally, wfi is treated as a nop during single-stepping and D-mode.
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@ -1047,7 +1018,7 @@ hazard3_priority_encode #(
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hazard3_priority_encode #(
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.W_REQ (16)
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) irq_priority (
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.req (mip_no_global[15:0] & mie[15:0]),
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.req (mip[15:0] & mie[15:0]),
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.gnt (standard_irq_num)
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);
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@ -1055,15 +1026,9 @@ hazard3_priority_encode #(
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// depending on dcsr.ebreakm.
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assign exception_req_any = except != EXCEPT_NONE && !(except == EXCEPT_EBREAK && dcsr_ebreakm);
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// Note when eivect=0 platform external interrupts also count as a standard
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// external interrupt, so the standard mapping (collapsed into a single
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// vector) always takes priority.
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wire [5:0] mcause_irq_num =
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standard_irq_active ? {2'h0, standard_irq_num} :
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external_irq_active ? {1'h0, external_irq_num} + 6'd16 : 6'd0;
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wire [5:0] mcause_irq_num = irq_active ? {2'h0, standard_irq_num} : 6'd0;
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wire [5:0] vector_sel =
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!exception_req_any && irq_vector_enable ? mcause_irq_num : 6'd0;
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wire [5:0] vector_sel = !exception_req_any && irq_vector_enable ? mcause_irq_num : 6'd0;
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assign trap_addr =
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except == EXCEPT_MRET ? mepc :
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@ -1077,7 +1042,7 @@ assign trap_is_irq = DEBUG_SUPPORT && (want_halt_except || want_halt_irq) ?
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// delay_irq_entry also applies to IRQ-like debug entries.
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assign trap_enter_vld =
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CSR_M_TRAP && (exception_req_any ||
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!delay_irq_entry && !debug_mode && (standard_irq_active || external_irq_active)) ||
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!delay_irq_entry && !debug_mode && irq_active) ||
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DEBUG_SUPPORT && (
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(!delay_irq_entry && want_halt_irq) || want_halt_except || pending_dbg_resume);
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@ -8,7 +8,7 @@ cd embench-iot
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# Make sure testbench is up to date
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make -C ../../tb_cxxrtl tb
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./build_all.py --arch riscv32 --chip hazard3 --board hazard3tb
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./benchmark_speed --target-module run_hazard3tb
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./benchmark_speed.py --target-module run_hazard3tb
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```
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The compiler specified in `config/riscv32/chips/hazard3/chip.cfg` is `/opt/riscv/unstable/bin/riscv32-unknown-elf-gcc`, which is where I have an unstable GCC 12 build installed on my machine. You need to have a recent upstream master build to support the Zba/Zbb/Zbc/Zbs instructions. If you don't care about these, you can use whatever `riscv32-unknown-elf` compiler you have, and also edit `cflags` in that `.cfg` file to not include the bitmanip extensions in `march`.
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