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Just use read_verilog; write_cxxrtl when building tb_cxxrtl

This commit is contained in:
Luke Wren 2021-07-22 17:30:30 +01:00
parent 8cdde82248
commit 5d2a562f65
1 changed files with 0 additions and 2 deletions
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2
test/sim/tb_cxxrtl/Makefile
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@ -22,8 +22,6 @@ SYNTH_CMD += chparam -set RESET_VECTOR $(CPU_RESET_VECTOR) $(TOP);
SYNTH_CMD += chparam -set REDUCED_BYPASS $(REDUCED_BYPASS) $(TOP);
SYNTH_CMD += chparam -set MULDIV_UNROLL $(MULDIV_UNROLL) $(TOP);
SYNTH_CMD += chparam -set MUL_FAST $(MUL_FAST) $(TOP);
SYNTH_CMD += hierarchy -top $(TOP); proc; opt_clean;
SYNTH_CMD += splitnets -driver;
SYNTH_CMD += write_cxxrtl dut.cpp
dut.cpp: