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Update ISA support in Readme

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Luke Wren 2021-12-04 23:49:35 +00:00
parent df658d86ff
commit 723016a739
1 changed files with 1 additions and 2 deletions
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@ -4,7 +4,7 @@ Hazard3 is a 3-stage RISC-V processor, implementing the `RV32I` instruction set
* `M`: integer multiply/divide/modulo * `M`: integer multiply/divide/modulo
* `C`: compressed instructions * `C`: compressed instructions
* `A` _(partial)_: load reserved/store conditional instructions, with AHB5 HEXCL/HEXOKAY signalling for global monitor queries * `A` : _(experimental)_ atomic memory operations, with AHB5 global exclusives
* `Zicsr`: CSR access * `Zicsr`: CSR access
* `Zba`: address generation * `Zba`: address generation
* `Zbb`: basic bit manipulation * `Zbb`: basic bit manipulation
@ -24,7 +24,6 @@ _Note: the bit manipulation instructions don't have upstream compliance tests at
The following are planned for future implementation: The following are planned for future implementation:
* Complete support for the `A` extension: atomic memory operations
* Debug trigger unit (breakpoint-only) * Debug trigger unit (breakpoint-only)
Hazard3 is still under development. Hazard3 is still under development.