colin
/
Hazard3
1
0
Fork 0
Code Issues Pull Requests Packages Projects Releases Wiki Activity

Update readme

This commit is contained in:
Luke Wren 2021-11-26 02:09:39 +00:00
parent 8398d7ecb6
commit 7410c52aac
1 changed files with 1 additions and 0 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

1
Readme.md
View File

@ -6,6 +6,7 @@ Hazard3 is a 3-stage RISC-V processor, providing the following architectural sup
* `M` extension: integer multiply/divide/modulo
* `C` extension: compressed instructions
* `Zicsr` extension: CSR access
* Tentatively the `Zba`, `Zbb`, `Zbc` and `Zbs` bitmanip extensions, though there are no upstream compliance tests for these as of yet
* M-mode privileged instructions `ECALL`, `EBREAK`, `MRET`
* The machine-mode (M-mode) privilege state, and standard M-mode CSRs
* Debug support, compliant with RISC-V debug specification version 0.13.2