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Fix a couple issues with trap exit, can now run add check with traps enabled (at low depth)

This commit is contained in:
Luke Wren 2021-05-23 06:40:44 +01:00
parent dec78a728d
commit 7a3ce494e4
3 changed files with 2 additions and 6 deletions
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2
hdl/hazard3_core.v
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@ -383,7 +383,7 @@ hazard3_csr #(
.trap_addr (x_trap_addr), .trap_addr (x_trap_addr),
.trap_enter_vld (x_trap_enter), .trap_enter_vld (x_trap_enter),
.trap_enter_rdy (x_trap_enter_rdy), .trap_enter_rdy (x_trap_enter_rdy),
.trap_exit (x_trap_exit), .trap_exit (x_trap_exit && !x_stall),
.trap_is_exception (x_trap_is_exception), .trap_is_exception (x_trap_is_exception),
.mepc_in (d_pc), .mepc_in (d_pc),
.mepc_out (x_mepc), .mepc_out (x_mepc),

1
hdl/hazard3_decode.v
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@ -262,6 +262,7 @@ always @ (*) begin
d_branchcond = BCOND_NEVER; d_branchcond = BCOND_NEVER;
d_csr_ren = 1'b0; d_csr_ren = 1'b0;
d_csr_wen = 1'b0; d_csr_wen = 1'b0;
d_except = EXCEPT_NONE;
if (EXTENSION_M) if (EXTENSION_M)
d_aluop = ALUOP_ADD; d_aluop = ALUOP_ADD;

5
hdl/hazard3_rvfi_monitor.vh
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@ -8,11 +8,6 @@
// //
// All modelling signals prefixed with rvfm (riscv-formal monitor) // All modelling signals prefixed with rvfm (riscv-formal monitor)
// FIXME!!!!!
always assume(!(x_trap_enter || x_trap_exit));
// ---------------------------------------------------------------------------- // ----------------------------------------------------------------------------
// Instruction monitor // Instruction monitor