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Hazard3
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Fix decompress of c.sb/c.sh 

Can now run CoreMark, Hazard3 sw testcases etc using core-v compiler
with Zcb enabled.
This commit is contained in:
Luke Wren 2023-03-16 20:27:21 +00:00
parent 59edb2fc5f
commit 99c0660c3e
2 changed files with 6 additions and 6 deletions
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2
Readme.md
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@ -11,7 +11,7 @@ Hazard3 is a 3-stage RISC-V processor, implementing the `RV32I` instruction set
* `Zbc`: carry-less multiplication
* `Zbs`: single-bit manipulation
* `Zbkb`: basic bit manipulation for scalar cryptography
* `Zcb`: basic additional compressed instructions *(experimental)*
* `Zcb`: basic additional compressed instructions
* Debug, Machine and User privilege/execution modes
* Privileged instructions `ECALL`, `EBREAK`, `MRET` and `WFI`
* Physical memory protection (PMP) with up to 16 naturally aligned regions

4
hdl/hazard3_instr_decompress.v
View File

@ -167,11 +167,11 @@ end else begin: instr_decompress
invalid = ~|EXTENSION_ZCB;
end
`RVOPC_C_SB: begin
instr_out = `RVOPC_NOZ_SB | rfmt_rd(rd_s) | rfmt_rs1(rs1_s) | imm_c_lb;
instr_out = `RVOPC_NOZ_SB | rfmt_rs2(rd_s) | rfmt_rs1(rs1_s) | imm_c_lb >> 13;
invalid = ~|EXTENSION_ZCB;
end
`RVOPC_C_SH: begin
instr_out = `RVOPC_NOZ_SH | rfmt_rd(rd_s) | rfmt_rs1(rs1_s) | imm_c_lh;
instr_out = `RVOPC_NOZ_SH | rfmt_rs2(rd_s) | rfmt_rs1(rs1_s) | imm_c_lh >> 13;
invalid = ~|EXTENSION_ZCB;
end
`RVOPC_C_ZEXT_B: begin