Add U bit to misa, and fix some broken debug tests (no hazard3 bugs)

2022-05-25 23:46:23 +01:00 · 2022-05-25 23:46:23 +01:00 · a17b941e38
parent 37f7588bad
commit a17b941e38
2 changed files with 4 additions and 2 deletions
--- a/hdl/hazard3_csr.v
+++ b/hdl/hazard3_csr.v
@ -478,7 +478,9 @@ always @ (*) begin

 			2'd0,              // Z, Y, no
 			|CSR_M_TRAP,       // X is set for our non-standard interrupt enable CSRs
-			10'd0,             // W...N, no
+			2'd0,              // V, W, no
+			|U_MODE,
+			7'd0,              // T...N, no
 			|EXTENSION_M,
 			3'd0,              // L...J, no
 			1'b1,              // Integer ISA
--- a/test/sim/riscv-tests/riscv-tests
+++ b/test/sim/riscv-tests/riscv-tests
@ -1 +1 @@
-Subproject commit 8be7e4362db52942cc9711c3af01937b39646c02
+Subproject commit 6fc7268b2cefe47616e692de665b6141c3050c9d