rvcpp sim: add A extension and M-mode traps
(now passes a lot of the Hazard3 tests)
This commit is contained in:
Luke Wren
parent
26d699e18c
commit
a536e3baa7
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@ -9,13 +9,16 @@
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#include "rv_opcodes.h"
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#include "rv_types.h"
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#include "rv_csr.h"
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#include "mem.h"
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// Minimal RISC-V interpreter, supporting:
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// - RV32I
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// - M
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// - A
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// - C (also called Zca)
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// - Zcmp
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// - M-mode traps
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// Use unsigned arithmetic everywhere, with explicit sign extension as required.
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static inline ux_t sext(ux_t bits, int sign_bit) {
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@ -137,57 +140,151 @@ static inline uint zcmp_s_mapping(uint s_raw) {
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return s_raw + 8 + 8 * ((s_raw & 0x6) != 0);
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}
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struct RVCSR {
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class RVCSR {
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// Current core privilege level (M/S/U)
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uint priv;
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ux_t mcycle;
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ux_t mstatus;
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ux_t mie;
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ux_t mip;
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ux_t mtvec;
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ux_t mscratch;
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ux_t mepc;
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ux_t mcause;
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public:
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enum {
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WRITE = 0,
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WRITE_SET = 1,
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WRITE_CLEAR = 2
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};
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enum {
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MSCRATCH = 0x340,
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MCYCLE = 0xb00,
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MTIME = 0xb01,
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MINSTRET = 0xb02
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};
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ux_t mcycle;
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ux_t mscratch;
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RVCSR(): mcycle(0), mscratch(0) {}
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RVCSR() {
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priv = 3;
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mcycle = 0;
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mstatus = 0;
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mie = 0;
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mip = 0;
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mtvec = 0;
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mscratch = 0;
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mepc = 0;
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mcause = 0;
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}
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void step() {++mcycle;}
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ux_t read(uint16_t addr, bool side_effect=true) {
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if (addr == MCYCLE || addr == MTIME || addr == MINSTRET)
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return mcycle;
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else if (addr == MSCRATCH)
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return mscratch;
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else
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return 0;
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// Returns None on permission/decode fail
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std::optional<ux_t> read(uint16_t addr, bool side_effect=true) {
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if (addr >= 1u << 12 || GETBITS(addr, 9, 8) > priv)
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return {};
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switch (addr) {
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case CSR_MISA: return 0x40101105; // RV32IMAC + U
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case CSR_MHARTID: return 0;
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case CSR_MARCHID: return 0;
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case CSR_MIMPID: return 0;
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case CSR_MVENDORID: return 0;
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case CSR_MSTATUS: return mstatus;
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case CSR_MIE: return mie;
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case CSR_MIP: return mip;
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case CSR_MTVEC: return mtvec;
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case CSR_MSCRATCH: return mscratch;
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case CSR_MEPC: return mepc;
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case CSR_MCAUSE: return mcause;
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case CSR_MTVAL: return 0;
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case CSR_MCYCLE: return mcycle;
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case CSR_MINSTRET: return mcycle;
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default: return {};
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}
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}
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void write(uint16_t addr, ux_t data, uint op=WRITE) {
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if (op == WRITE_CLEAR)
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data = read(addr, false) & ~data;
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else if (op == WRITE_SET)
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data = read(addr, false) | data;
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if (addr == MCYCLE)
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mcycle = data;
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else if (addr == MSCRATCH)
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mscratch = data;
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// Returns false on permission/decode fail
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bool write(uint16_t addr, ux_t data, uint op=WRITE) {
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if (addr >= 1u << 12 || GETBITS(addr, 9, 8) > priv)
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return false;
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if (addr >= 1u << 12)
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if (op == WRITE_CLEAR || op == WRITE_SET) {
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std::optional<ux_t> rdata = read(addr, false);
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if (!rdata)
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return false;
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if (op == WRITE_CLEAR)
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data &= ~*rdata;
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else
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data |= *rdata;
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}
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switch (addr) {
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case CSR_MISA: break;
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case CSR_MHARTID: break;
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case CSR_MARCHID: break;
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case CSR_MIMPID: break;
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case CSR_MSTATUS: mstatus = data; break;
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case CSR_MIE: mie = data; break;
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case CSR_MIP: break;
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case CSR_MTVEC: mtvec = data & 0xfffffffdu; break;
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case CSR_MSCRATCH: mscratch = data; break;
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case CSR_MEPC: mepc = data & 0xfffffffeu; break;
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case CSR_MCAUSE: mcause = data & 0x800000ffu; break;
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case CSR_MTVAL: break;
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case CSR_MCYCLE: mcycle = data; break;
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case CSR_MINSTRET: mcycle = data; break;
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default: return false;
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}
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return true;
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}
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// Update trap state (including change of privilege level), return trap target PC
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ux_t trap_enter(uint xcause, ux_t xepc) {
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mstatus = (mstatus & ~MSTATUS_MPP) | (priv << 11);
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priv = PRV_M;
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if (mstatus & MSTATUS_MIE)
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mstatus |= MSTATUS_MPIE;
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mstatus &= ~MSTATUS_MIE;
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mcause = xcause;
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mepc = xepc;
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if ((mtvec & 0x1) && (xcause & (1u << 31))) {
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return (mtvec & -2) + 4 * (xcause & ~(1u << 31));
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} else {
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return mtvec & -2;
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}
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}
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// Update trap state, return mepc:
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ux_t trap_mret() {
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priv = GETBITS(mstatus, 12, 11);
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if (mstatus & MSTATUS_MPIE)
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mstatus |= MSTATUS_MIE;
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mstatus &= ~MSTATUS_MPIE;
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return mepc;
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}
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uint getpriv() {
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return priv;
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}
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};
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struct RVCore {
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std::array<ux_t, 32> regs;
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ux_t pc;
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RVCSR csr;
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bool load_reserved;
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RVCore(ux_t reset_vector=0x40) {
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std::fill(std::begin(regs), std::end(regs), 0);
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pc = reset_vector;
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load_reserved = false;
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}
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enum {
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@ -196,6 +293,7 @@ struct RVCore {
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OPC_OP_IMM = 0b00'100,
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OPC_AUIPC = 0b00'101,
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OPC_STORE = 0b01'000,
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OPC_AMO = 0b01'011,
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OPC_OP = 0b01'100,
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OPC_LUI = 0b01'101,
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OPC_BRANCH = 0b11'000,
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@ -208,12 +306,8 @@ struct RVCore {
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uint32_t instr = mem.r16(pc) | (mem.r16(pc + 2) << 16);
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std::optional<ux_t> rd_wdata;
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std::optional<ux_t> pc_wdata;
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uint regnum_rs1 = instr >> 15 & 0x1f;
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uint regnum_rs2 = instr >> 20 & 0x1f;
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uint regnum_rd = instr >> 7 & 0x1f;
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ux_t rs1 = regs[regnum_rs1];
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ux_t rs2 = regs[regnum_rs2];
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bool instr_invalid = false;
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uint regnum_rd = 0;
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std::optional<uint> exception_cause;
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uint opc = instr >> 2 & 0x1f;
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uint funct3 = instr >> 12 & 0x7;
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@ -221,6 +315,11 @@ struct RVCore {
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if ((instr & 0x3) == 0x3) {
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// 32-bit instruction
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uint regnum_rs1 = instr >> 15 & 0x1f;
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uint regnum_rs2 = instr >> 20 & 0x1f;
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regnum_rd = instr >> 7 & 0x1f;
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ux_t rs1 = regs[regnum_rs1];
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ux_t rs2 = regs[regnum_rs2];
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switch (opc) {
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case OPC_OP: {
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@ -242,7 +341,7 @@ struct RVCore {
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else if (funct3 == 0b111)
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rd_wdata = rs1 & rs2;
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else
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instr_invalid = true;
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exception_cause = XCAUSE_INSTR_ILLEGAL;
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}
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else if (funct7 == 0b01'00000) {
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if (funct3 == 0b000)
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@ -250,7 +349,7 @@ struct RVCore {
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else if (funct3 == 0b101)
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rd_wdata = (sx_t)rs1 >> (rs2 & 0x1f);
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else
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instr_invalid = true;
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exception_cause = XCAUSE_INSTR_ILLEGAL;
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}
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else if (funct7 == 0b00'00001) {
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if (funct3 < 0b100) {
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@ -292,7 +391,7 @@ struct RVCore {
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}
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}
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else {
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instr_invalid = true;
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exception_cause = XCAUSE_INSTR_ILLEGAL;
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}
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break;
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}
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@ -323,11 +422,11 @@ struct RVCore {
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rd_wdata = (sx_t)rs1 >> regnum_rs2;
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}
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else {
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instr_invalid = true;
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exception_cause = XCAUSE_INSTR_ILLEGAL;
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}
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}
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else {
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instr_invalid = true;
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exception_cause = XCAUSE_INSTR_ILLEGAL;
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}
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break;
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}
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@ -342,8 +441,8 @@ struct RVCore {
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else if ((funct3 & 0b110) == 0b110)
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taken = rs1 < rs2;
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else
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instr_invalid = true;
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if (!instr_invalid && funct3 & 0b001)
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exception_cause = XCAUSE_INSTR_ILLEGAL;
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if (!exception_cause && funct3 & 0b001)
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taken = !taken;
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if (taken)
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pc_wdata = target;
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@ -352,31 +451,109 @@ struct RVCore {
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case OPC_LOAD: {
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ux_t load_addr = rs1 + imm_i(instr);
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if (funct3 == 0b000)
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if (funct3 == 0b000) {
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rd_wdata = sext(mem.r8(load_addr), 7);
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else if (funct3 == 0b001)
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rd_wdata = sext(mem.r16(load_addr), 15);
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else if (funct3 == 0b010)
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rd_wdata = mem.r32(load_addr);
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else if (funct3 == 0b100)
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} else if (funct3 == 0b001) {
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if (load_addr & 0x1)
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exception_cause = XCAUSE_LOAD_ALIGN;
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else
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rd_wdata = sext(mem.r16(load_addr), 15);
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} else if (funct3 == 0b010) {
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if (load_addr & 0x3)
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exception_cause = XCAUSE_LOAD_ALIGN;
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else
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rd_wdata = mem.r32(load_addr);
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} else if (funct3 == 0b100) {
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rd_wdata = mem.r8(load_addr);
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else if (funct3 == 0b101)
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rd_wdata = mem.r16(load_addr);
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else
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instr_invalid = true;
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} else if (funct3 == 0b101) {
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if (load_addr & 0x1)
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exception_cause = XCAUSE_LOAD_ALIGN;
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else
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rd_wdata = mem.r16(load_addr);
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} else {
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exception_cause = XCAUSE_INSTR_ILLEGAL;
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}
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break;
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}
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case OPC_STORE: {
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ux_t store_addr = rs1 + imm_s(instr);
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if (funct3 == 0b000)
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if (funct3 == 0b000) {
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mem.w8(store_addr, rs2 & 0xffu);
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else if (funct3 == 0b001)
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mem.w16(store_addr, rs2 & 0xffffu);
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else if (funct3 == 0b010)
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mem.w32(store_addr, rs2);
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else
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instr_invalid = true;
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} else if (funct3 == 0b001) {
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if (store_addr & 0x1)
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exception_cause = XCAUSE_STORE_ALIGN;
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else
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mem.w16(store_addr, rs2 & 0xffffu);
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} else if (funct3 == 0b010) {
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if (store_addr & 0x3)
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exception_cause = XCAUSE_STORE_ALIGN;
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else
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mem.w32(store_addr, rs2);
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} else {
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exception_cause = XCAUSE_INSTR_ILLEGAL;
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}
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break;
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}
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case OPC_AMO: {
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if (RVOPC_MATCH(instr, LR_W)) {
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if (rs1 & 0x3) {
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exception_cause = XCAUSE_LOAD_ALIGN;
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} else {
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rd_wdata = mem.r32(rs1);
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load_reserved = true;
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}
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} else if (RVOPC_MATCH(instr, SC_W)) {
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if (rs1 & 0x3) {
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exception_cause = XCAUSE_STORE_ALIGN;
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} else {
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if (load_reserved) {
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load_reserved = false;
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mem.w32(rs1, rs2);
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rd_wdata = 0;
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} else {
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rd_wdata = 1;
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}
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}
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} else if (RVOPC_MATCH(instr, AMOSWAP_W)) {
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if (rs1 & 0x3) {
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exception_cause = XCAUSE_STORE_ALIGN;
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} else {
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rd_wdata = mem.r32(rs1);
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mem.w32(rs1, rs2);
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}
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} else if (
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RVOPC_MATCH(instr, AMOSWAP_W) ||
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RVOPC_MATCH(instr, AMOADD_W) ||
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RVOPC_MATCH(instr, AMOXOR_W) ||
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RVOPC_MATCH(instr, AMOAND_W) ||
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RVOPC_MATCH(instr, AMOOR_W) ||
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RVOPC_MATCH(instr, AMOMIN_W) ||
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RVOPC_MATCH(instr, AMOMAX_W) ||
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RVOPC_MATCH(instr, AMOMINU_W) ||
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RVOPC_MATCH(instr, AMOMAXU_W)) {
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if (rs1 & 0x3) {
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exception_cause = XCAUSE_STORE_ALIGN;
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} else {
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rd_wdata = mem.r32(rs1);
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switch (instr & RVOPC_AMOSWAP_W_MASK) {
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case RVOPC_AMOSWAP_W_BITS: mem.w32(rs1, *rd_wdata); break;
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case RVOPC_AMOADD_W_BITS: mem.w32(rs1, *rd_wdata + rs2); break;
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case RVOPC_AMOXOR_W_BITS: mem.w32(rs1, *rd_wdata ^ rs2); break;
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case RVOPC_AMOAND_W_BITS: mem.w32(rs1, *rd_wdata & rs2); break;
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case RVOPC_AMOOR_W_BITS: mem.w32(rs1, *rd_wdata | rs2); break;
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case RVOPC_AMOMIN_W_BITS: mem.w32(rs1, (sx_t)*rd_wdata < (sx_t)rs2 ? *rd_wdata : rs2); break;
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case RVOPC_AMOMAX_W_BITS: mem.w32(rs1, (sx_t)*rd_wdata > (sx_t)rs2 ? *rd_wdata : rs2); break;
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case RVOPC_AMOMINU_W_BITS: mem.w32(rs1, *rd_wdata < rs2 ? *rd_wdata : rs2); break;
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case RVOPC_AMOMAXU_W_BITS: mem.w32(rs1, *rd_wdata > rs2 ? *rd_wdata : rs2); break;
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default: assert(false); break;
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}
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}
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} else {
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exception_cause = XCAUSE_INSTR_ILLEGAL;
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}
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break;
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}
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@ -403,10 +580,17 @@ struct RVCore {
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if (funct3 >= 0b001 && funct3 <= 0b011) {
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// csrrw, csrrs, csrrc
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uint write_op = funct3 - 0b001;
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if (write_op != RVCSR::WRITE || regnum_rd != 0)
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if (write_op != RVCSR::WRITE || regnum_rd != 0) {
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rd_wdata = csr.read(csr_addr);
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if (write_op == RVCSR::WRITE || regnum_rs1 != 0)
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csr.write(csr_addr, rs1, write_op);
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if (!rd_wdata) {
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exception_cause = XCAUSE_INSTR_ILLEGAL;
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}
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}
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else if (write_op == RVCSR::WRITE || regnum_rs1 != 0) {
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if (!csr.write(csr_addr, rs1, write_op)) {
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exception_cause = XCAUSE_INSTR_ILLEGAL;
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}
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}
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}
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else if (funct3 >= 0b101 && funct3 <= 0b111) {
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// csrrwi, csrrsi, csrrci
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@ -415,22 +599,31 @@ struct RVCore {
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rd_wdata = csr.read(csr_addr);
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if (write_op == RVCSR::WRITE || regnum_rs1 != 0)
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csr.write(csr_addr, regnum_rs1, write_op);
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}
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else {
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instr_invalid = true;
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} else if (RVOPC_MATCH(instr, MRET)) {
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if (csr.getpriv() == PRV_M) {
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pc_wdata = csr.trap_mret();
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} else {
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exception_cause = XCAUSE_INSTR_ILLEGAL;
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}
|
||||
} else if (RVOPC_MATCH(instr, ECALL)) {
|
||||
exception_cause = XCAUSE_ECALL_U + csr.getpriv();
|
||||
} else if (RVOPC_MATCH(instr, EBREAK)) {
|
||||
exception_cause = XCAUSE_EBREAK;
|
||||
} else {
|
||||
exception_cause = XCAUSE_INSTR_ILLEGAL;
|
||||
}
|
||||
break;
|
||||
}
|
||||
|
||||
default:
|
||||
instr_invalid = true;
|
||||
exception_cause = XCAUSE_INSTR_ILLEGAL;
|
||||
break;
|
||||
}
|
||||
} else {
|
||||
regnum_rd = 0;
|
||||
// 16-bit instructions
|
||||
} else if ((instr & 0x3) == 0x0) {
|
||||
// RVC Quadrant 00:
|
||||
if (RVOPC_MATCH(instr, C_ADDI4SPN)) {
|
||||
if (RVOPC_MATCH(instr, ILLEGAL16)) {
|
||||
exception_cause = XCAUSE_INSTR_ILLEGAL;
|
||||
} else if (RVOPC_MATCH(instr, C_ADDI4SPN)) {
|
||||
regnum_rd = c_rs2_s(instr);
|
||||
rd_wdata = regs[2]
|
||||
+ (GETBITS(instr, 12, 11) << 4)
|
||||
|
|
@ -450,8 +643,12 @@ struct RVCore {
|
|||
+ (GETBITS(instr, 12, 10) << 3)
|
||||
+ (GETBIT(instr, 5) << 6);
|
||||
mem.w32(addr, regs[c_rs2_s(instr)]);
|
||||
} else {
|
||||
exception_cause = XCAUSE_INSTR_ILLEGAL;
|
||||
}
|
||||
} else if ((instr & 0x3) == 0x1) {
|
||||
// RVC Quadrant 01:
|
||||
} else if (RVOPC_MATCH(instr, C_ADDI)) {
|
||||
if (RVOPC_MATCH(instr, C_ADDI)) {
|
||||
regnum_rd = c_rs1_l(instr);
|
||||
rd_wdata = regs[c_rs1_l(instr)] + imm_ci(instr);
|
||||
} else if (RVOPC_MATCH(instr, C_JAL)) {
|
||||
|
|
@ -506,8 +703,12 @@ struct RVCore {
|
|||
if (regs[c_rs1_s(instr)] != 0) {
|
||||
pc_wdata = pc + imm_cb(instr);
|
||||
}
|
||||
} else {
|
||||
exception_cause = XCAUSE_INSTR_ILLEGAL;
|
||||
}
|
||||
} else {
|
||||
// RVC Quadrant 10:
|
||||
} else if (RVOPC_MATCH(instr, C_SLLI)) {
|
||||
if (RVOPC_MATCH(instr, C_SLLI)) {
|
||||
regnum_rd = c_rs1_l(instr);
|
||||
rd_wdata = regs[regnum_rd] << GETBITS(instr, 6, 2);
|
||||
} else if (RVOPC_MATCH(instr, C_MV)) {
|
||||
|
|
@ -520,10 +721,15 @@ struct RVCore {
|
|||
}
|
||||
} else if (RVOPC_MATCH(instr, C_ADD)) {
|
||||
if (c_rs2_l(instr) == 0) {
|
||||
// c.jalr
|
||||
pc_wdata = regs[c_rs1_l(instr)] & -2u;
|
||||
regnum_rd = 1;
|
||||
rd_wdata = pc + 2;
|
||||
if (c_rs1_l(instr) == 0) {
|
||||
// c.ebreak
|
||||
exception_cause = XCAUSE_EBREAK;
|
||||
} else {
|
||||
// c.jalr
|
||||
pc_wdata = regs[c_rs1_l(instr)] & -2u;
|
||||
regnum_rd = 1;
|
||||
rd_wdata = pc + 2;
|
||||
}
|
||||
} else {
|
||||
regnum_rd = c_rs1_l(instr);
|
||||
rd_wdata = regs[c_rs1_l(instr)] + regs[c_rs2_l(instr)];
|
||||
|
|
@ -574,11 +780,10 @@ struct RVCore {
|
|||
regs[10] = regs[zcmp_s_mapping(GETBITS(instr, 9, 7))];
|
||||
regs[11] = regs[zcmp_s_mapping(GETBITS(instr, 4, 2))];
|
||||
} else {
|
||||
instr_invalid = true;
|
||||
exception_cause = XCAUSE_INSTR_ILLEGAL;
|
||||
}
|
||||
}
|
||||
if (instr_invalid)
|
||||
printf("Invalid instr %08x at %08x\n", instr, pc);
|
||||
|
||||
|
||||
if (trace) {
|
||||
printf("%08x: ", pc);
|
||||
|
|
@ -599,6 +804,13 @@ struct RVCore {
|
|||
}
|
||||
}
|
||||
|
||||
if (exception_cause) {
|
||||
pc_wdata = csr.trap_enter(*exception_cause, pc);
|
||||
if (trace) {
|
||||
printf("Trap cause %2u: pc <- %08x\n", *exception_cause, *pc_wdata);
|
||||
}
|
||||
}
|
||||
|
||||
if (pc_wdata)
|
||||
pc = *pc_wdata;
|
||||
else
|
||||
|
|
|
|||
|
|
@ -0,0 +1,426 @@
|
|||
#ifndef _RVCPP_RV_CSR_H
|
||||
#define _RVCPP_RV_CSR_H
|
||||
|
||||
// Adapted in part from encoding.h in riscv-test-env
|
||||
// Original licence/copyright notice follows:
|
||||
|
||||
/*
|
||||
* Copyright (c) 2012-2015, The Regents of the University of California (Regents).
|
||||
* All Rights Reserved.
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions are met:
|
||||
* 1. Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer.
|
||||
* 2. Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in the
|
||||
* documentation and/or other materials provided with the distribution.
|
||||
* 3. Neither the name of the Regents nor the
|
||||
* names of its contributors may be used to endorse or promote products
|
||||
* derived from this software without specific prior written permission.
|
||||
* IN NO EVENT SHALL REGENTS BE LIABLE TO ANY PARTY FOR DIRECT, INDIRECT,
|
||||
* SPECIAL, INCIDENTAL, OR CONSEQUENTIAL DAMAGES, INCLUDING LOST PROFITS, ARISING
|
||||
* OUT OF THE USE OF THIS SOFTWARE AND ITS DOCUMENTATION, EVEN IF REGENTS HAS
|
||||
* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
* REGENTS SPECIFICALLY DISCLAIMS ANY WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
|
||||
* THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
|
||||
* PURPOSE. THE SOFTWARE AND ACCOMPANYING DOCUMENTATION, IF ANY, PROVIDED
|
||||
* HEREUNDER IS PROVIDED "AS IS". REGENTS HAS NO OBLIGATION TO PROVIDE
|
||||
* MAINTENANCE, SUPPORT, UPDATES, ENHANCEMENTS, OR MODIFICATIONS.
|
||||
|
||||
*/
|
||||
|
||||
#define XCAUSE_INSTR_MISALIGN 0x0
|
||||
#define XCAUSE_INSTR_FAULT 0x1
|
||||
#define XCAUSE_INSTR_ILLEGAL 0x2
|
||||
#define XCAUSE_EBREAK 0x3
|
||||
#define XCAUSE_LOAD_ALIGN 0x4
|
||||
#define XCAUSE_LOAD_FAULT 0x5
|
||||
#define XCAUSE_STORE_ALIGN 0x6
|
||||
#define XCAUSE_STORE_FAULT 0x7
|
||||
#define XCAUSE_ECALL_U 0x8
|
||||
#define XCAUSE_ECALL_S 0x9
|
||||
#define XCAUSE_ECALL_M 0xb
|
||||
|
||||
#define MSTATUS_UIE 0x00000001
|
||||
#define MSTATUS_SIE 0x00000002
|
||||
#define MSTATUS_HIE 0x00000004
|
||||
#define MSTATUS_MIE 0x00000008
|
||||
#define MSTATUS_UPIE 0x00000010
|
||||
#define MSTATUS_SPIE 0x00000020
|
||||
#define MSTATUS_HPIE 0x00000040
|
||||
#define MSTATUS_MPIE 0x00000080
|
||||
#define MSTATUS_SPP 0x00000100
|
||||
#define MSTATUS_HPP 0x00000600
|
||||
#define MSTATUS_MPP 0x00001800
|
||||
#define MSTATUS_FS 0x00006000
|
||||
#define MSTATUS_XS 0x00018000
|
||||
#define MSTATUS_MPRV 0x00020000
|
||||
#define MSTATUS_SUM 0x00040000
|
||||
#define MSTATUS_MXR 0x00080000
|
||||
#define MSTATUS_TVM 0x00100000
|
||||
#define MSTATUS_TW 0x00200000
|
||||
#define MSTATUS_TSR 0x00400000
|
||||
#define MSTATUS32_SD 0x80000000
|
||||
#define MSTATUS_UXL 0x0000000300000000
|
||||
#define MSTATUS_SXL 0x0000000C00000000
|
||||
#define MSTATUS64_SD 0x8000000000000000
|
||||
|
||||
#define SSTATUS_UIE 0x00000001
|
||||
#define SSTATUS_SIE 0x00000002
|
||||
#define SSTATUS_UPIE 0x00000010
|
||||
#define SSTATUS_SPIE 0x00000020
|
||||
#define SSTATUS_SPP 0x00000100
|
||||
#define SSTATUS_FS 0x00006000
|
||||
#define SSTATUS_XS 0x00018000
|
||||
#define SSTATUS_SUM 0x00040000
|
||||
#define SSTATUS_MXR 0x00080000
|
||||
#define SSTATUS32_SD 0x80000000
|
||||
#define SSTATUS_UXL 0x0000000300000000
|
||||
#define SSTATUS64_SD 0x8000000000000000
|
||||
|
||||
#define DCSR_XDEBUGVER (3U<<30)
|
||||
#define DCSR_NDRESET (1<<29)
|
||||
#define DCSR_FULLRESET (1<<28)
|
||||
#define DCSR_EBREAKM (1<<15)
|
||||
#define DCSR_EBREAKH (1<<14)
|
||||
#define DCSR_EBREAKS (1<<13)
|
||||
#define DCSR_EBREAKU (1<<12)
|
||||
#define DCSR_STOPCYCLE (1<<10)
|
||||
#define DCSR_STOPTIME (1<<9)
|
||||
#define DCSR_CAUSE (7<<6)
|
||||
#define DCSR_DEBUGINT (1<<5)
|
||||
#define DCSR_HALT (1<<3)
|
||||
#define DCSR_STEP (1<<2)
|
||||
#define DCSR_PRV (3<<0)
|
||||
|
||||
#define DCSR_CAUSE_NONE 0
|
||||
#define DCSR_CAUSE_SWBP 1
|
||||
#define DCSR_CAUSE_HWBP 2
|
||||
#define DCSR_CAUSE_DEBUGINT 3
|
||||
#define DCSR_CAUSE_STEP 4
|
||||
#define DCSR_CAUSE_HALT 5
|
||||
|
||||
#define MCONTROL_TYPE(xlen) (0xfULL<<((xlen)-4))
|
||||
#define MCONTROL_DMODE(xlen) (1ULL<<((xlen)-5))
|
||||
#define MCONTROL_MASKMAX(xlen) (0x3fULL<<((xlen)-11))
|
||||
|
||||
#define MCONTROL_SELECT (1<<19)
|
||||
#define MCONTROL_TIMING (1<<18)
|
||||
#define MCONTROL_ACTION (0x3f<<12)
|
||||
#define MCONTROL_CHAIN (1<<11)
|
||||
#define MCONTROL_MATCH (0xf<<7)
|
||||
#define MCONTROL_M (1<<6)
|
||||
#define MCONTROL_H (1<<5)
|
||||
#define MCONTROL_S (1<<4)
|
||||
#define MCONTROL_U (1<<3)
|
||||
#define MCONTROL_EXECUTE (1<<2)
|
||||
#define MCONTROL_STORE (1<<1)
|
||||
#define MCONTROL_LOAD (1<<0)
|
||||
|
||||
#define MCONTROL_TYPE_NONE 0
|
||||
#define MCONTROL_TYPE_MATCH 2
|
||||
|
||||
#define MCONTROL_ACTION_DEBUG_EXCEPTION 0
|
||||
#define MCONTROL_ACTION_DEBUG_MODE 1
|
||||
#define MCONTROL_ACTION_TRACE_START 2
|
||||
#define MCONTROL_ACTION_TRACE_STOP 3
|
||||
#define MCONTROL_ACTION_TRACE_EMIT 4
|
||||
|
||||
#define MCONTROL_MATCH_EQUAL 0
|
||||
#define MCONTROL_MATCH_NAPOT 1
|
||||
#define MCONTROL_MATCH_GE 2
|
||||
#define MCONTROL_MATCH_LT 3
|
||||
#define MCONTROL_MATCH_MASK_LOW 4
|
||||
#define MCONTROL_MATCH_MASK_HIGH 5
|
||||
|
||||
#define MIP_SSIP (1 << IRQ_S_SOFT)
|
||||
#define MIP_HSIP (1 << IRQ_H_SOFT)
|
||||
#define MIP_MSIP (1 << IRQ_M_SOFT)
|
||||
#define MIP_STIP (1 << IRQ_S_TIMER)
|
||||
#define MIP_HTIP (1 << IRQ_H_TIMER)
|
||||
#define MIP_MTIP (1 << IRQ_M_TIMER)
|
||||
#define MIP_SEIP (1 << IRQ_S_EXT)
|
||||
#define MIP_HEIP (1 << IRQ_H_EXT)
|
||||
#define MIP_MEIP (1 << IRQ_M_EXT)
|
||||
|
||||
#define SIP_SSIP MIP_SSIP
|
||||
#define SIP_STIP MIP_STIP
|
||||
|
||||
#define PRV_U 0
|
||||
#define PRV_S 1
|
||||
#define PRV_H 2
|
||||
#define PRV_M 3
|
||||
|
||||
#define SATP32_MODE 0x80000000
|
||||
#define SATP32_ASID 0x7FC00000
|
||||
#define SATP32_PPN 0x003FFFFF
|
||||
#define SATP64_MODE 0xF000000000000000
|
||||
#define SATP64_ASID 0x0FFFF00000000000
|
||||
#define SATP64_PPN 0x00000FFFFFFFFFFF
|
||||
|
||||
#define SATP_MODE_OFF 0
|
||||
#define SATP_MODE_SV32 1
|
||||
#define SATP_MODE_SV39 8
|
||||
#define SATP_MODE_SV48 9
|
||||
#define SATP_MODE_SV57 10
|
||||
#define SATP_MODE_SV64 11
|
||||
|
||||
#define PMP_R 0x01
|
||||
#define PMP_W 0x02
|
||||
#define PMP_X 0x04
|
||||
#define PMP_A 0x18
|
||||
#define PMP_L 0x80
|
||||
#define PMP_SHIFT 2
|
||||
|
||||
#define PMP_TOR 0x08
|
||||
#define PMP_NA4 0x10
|
||||
#define PMP_NAPOT 0x18
|
||||
|
||||
#define IRQ_S_SOFT 1
|
||||
#define IRQ_H_SOFT 2
|
||||
#define IRQ_M_SOFT 3
|
||||
#define IRQ_S_TIMER 5
|
||||
#define IRQ_H_TIMER 6
|
||||
#define IRQ_M_TIMER 7
|
||||
#define IRQ_S_EXT 9
|
||||
#define IRQ_H_EXT 10
|
||||
#define IRQ_M_EXT 11
|
||||
#define IRQ_COP 12
|
||||
#define IRQ_HOST 13
|
||||
|
||||
#define DEFAULT_RSTVEC 0x00001000
|
||||
#define CLINT_BASE 0x02000000
|
||||
#define CLINT_SIZE 0x000c0000
|
||||
#define EXT_IO_BASE 0x40000000
|
||||
#define DRAM_BASE 0x80000000
|
||||
|
||||
// page table entry (PTE) fields
|
||||
#define PTE_V 0x001 // Valid
|
||||
#define PTE_R 0x002 // Read
|
||||
#define PTE_W 0x004 // Write
|
||||
#define PTE_X 0x008 // Execute
|
||||
#define PTE_U 0x010 // User
|
||||
#define PTE_G 0x020 // Global
|
||||
#define PTE_A 0x040 // Accessed
|
||||
#define PTE_D 0x080 // Dirty
|
||||
#define PTE_SOFT 0x300 // Reserved for Software
|
||||
|
||||
#define PTE_PPN_SHIFT 10
|
||||
|
||||
#define PTE_TABLE(PTE) (((PTE) & (PTE_V | PTE_R | PTE_W | PTE_X)) == PTE_V)
|
||||
|
||||
#define CSR_FFLAGS 0x1
|
||||
#define CSR_FRM 0x2
|
||||
#define CSR_FCSR 0x3
|
||||
#define CSR_CYCLE 0xc00
|
||||
#define CSR_TIME 0xc01
|
||||
#define CSR_INSTRET 0xc02
|
||||
#define CSR_HPMCOUNTER3 0xc03
|
||||
#define CSR_HPMCOUNTER4 0xc04
|
||||
#define CSR_HPMCOUNTER5 0xc05
|
||||
#define CSR_HPMCOUNTER6 0xc06
|
||||
#define CSR_HPMCOUNTER7 0xc07
|
||||
#define CSR_HPMCOUNTER8 0xc08
|
||||
#define CSR_HPMCOUNTER9 0xc09
|
||||
#define CSR_HPMCOUNTER10 0xc0a
|
||||
#define CSR_HPMCOUNTER11 0xc0b
|
||||
#define CSR_HPMCOUNTER12 0xc0c
|
||||
#define CSR_HPMCOUNTER13 0xc0d
|
||||
#define CSR_HPMCOUNTER14 0xc0e
|
||||
#define CSR_HPMCOUNTER15 0xc0f
|
||||
#define CSR_HPMCOUNTER16 0xc10
|
||||
#define CSR_HPMCOUNTER17 0xc11
|
||||
#define CSR_HPMCOUNTER18 0xc12
|
||||
#define CSR_HPMCOUNTER19 0xc13
|
||||
#define CSR_HPMCOUNTER20 0xc14
|
||||
#define CSR_HPMCOUNTER21 0xc15
|
||||
#define CSR_HPMCOUNTER22 0xc16
|
||||
#define CSR_HPMCOUNTER23 0xc17
|
||||
#define CSR_HPMCOUNTER24 0xc18
|
||||
#define CSR_HPMCOUNTER25 0xc19
|
||||
#define CSR_HPMCOUNTER26 0xc1a
|
||||
#define CSR_HPMCOUNTER27 0xc1b
|
||||
#define CSR_HPMCOUNTER28 0xc1c
|
||||
#define CSR_HPMCOUNTER29 0xc1d
|
||||
#define CSR_HPMCOUNTER30 0xc1e
|
||||
#define CSR_HPMCOUNTER31 0xc1f
|
||||
#define CSR_SSTATUS 0x100
|
||||
#define CSR_SIE 0x104
|
||||
#define CSR_STVEC 0x105
|
||||
#define CSR_SCOUNTEREN 0x106
|
||||
#define CSR_SSCRATCH 0x140
|
||||
#define CSR_SEPC 0x141
|
||||
#define CSR_SCAUSE 0x142
|
||||
#define CSR_STVAL 0x143
|
||||
#define CSR_SIP 0x144
|
||||
#define CSR_SATP 0x180
|
||||
#define CSR_MSTATUS 0x300
|
||||
#define CSR_MISA 0x301
|
||||
#define CSR_MEDELEG 0x302
|
||||
#define CSR_MIDELEG 0x303
|
||||
#define CSR_MIE 0x304
|
||||
#define CSR_MTVEC 0x305
|
||||
#define CSR_MCOUNTEREN 0x306
|
||||
#define CSR_MSCRATCH 0x340
|
||||
#define CSR_MEPC 0x341
|
||||
#define CSR_MCAUSE 0x342
|
||||
#define CSR_MTVAL 0x343
|
||||
#define CSR_MIP 0x344
|
||||
#define CSR_PMPCFG0 0x3a0
|
||||
#define CSR_PMPCFG1 0x3a1
|
||||
#define CSR_PMPCFG2 0x3a2
|
||||
#define CSR_PMPCFG3 0x3a3
|
||||
#define CSR_PMPADDR0 0x3b0
|
||||
#define CSR_PMPADDR1 0x3b1
|
||||
#define CSR_PMPADDR2 0x3b2
|
||||
#define CSR_PMPADDR3 0x3b3
|
||||
#define CSR_PMPADDR4 0x3b4
|
||||
#define CSR_PMPADDR5 0x3b5
|
||||
#define CSR_PMPADDR6 0x3b6
|
||||
#define CSR_PMPADDR7 0x3b7
|
||||
#define CSR_PMPADDR8 0x3b8
|
||||
#define CSR_PMPADDR9 0x3b9
|
||||
#define CSR_PMPADDR10 0x3ba
|
||||
#define CSR_PMPADDR11 0x3bb
|
||||
#define CSR_PMPADDR12 0x3bc
|
||||
#define CSR_PMPADDR13 0x3bd
|
||||
#define CSR_PMPADDR14 0x3be
|
||||
#define CSR_PMPADDR15 0x3bf
|
||||
#define CSR_TSELECT 0x7a0
|
||||
#define CSR_TDATA1 0x7a1
|
||||
#define CSR_TDATA2 0x7a2
|
||||
#define CSR_TDATA3 0x7a3
|
||||
#define CSR_DCSR 0x7b0
|
||||
#define CSR_DPC 0x7b1
|
||||
#define CSR_DSCRATCH 0x7b2
|
||||
#define CSR_MCYCLE 0xb00
|
||||
#define CSR_MINSTRET 0xb02
|
||||
#define CSR_MHPMCOUNTER3 0xb03
|
||||
#define CSR_MHPMCOUNTER4 0xb04
|
||||
#define CSR_MHPMCOUNTER5 0xb05
|
||||
#define CSR_MHPMCOUNTER6 0xb06
|
||||
#define CSR_MHPMCOUNTER7 0xb07
|
||||
#define CSR_MHPMCOUNTER8 0xb08
|
||||
#define CSR_MHPMCOUNTER9 0xb09
|
||||
#define CSR_MHPMCOUNTER10 0xb0a
|
||||
#define CSR_MHPMCOUNTER11 0xb0b
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#define CSR_MHPMCOUNTER12 0xb0c
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#define CSR_MHPMCOUNTER13 0xb0d
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#define CSR_MHPMCOUNTER14 0xb0e
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#define CSR_MHPMCOUNTER15 0xb0f
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#define CSR_MHPMCOUNTER16 0xb10
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#define CSR_MHPMCOUNTER17 0xb11
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#define CSR_MHPMCOUNTER18 0xb12
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#define CSR_MHPMCOUNTER19 0xb13
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#define CSR_MHPMCOUNTER20 0xb14
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#define CSR_MHPMCOUNTER21 0xb15
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#define CSR_MHPMCOUNTER22 0xb16
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#define CSR_MHPMCOUNTER23 0xb17
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#define CSR_MHPMCOUNTER24 0xb18
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#define CSR_MHPMCOUNTER25 0xb19
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#define CSR_MHPMCOUNTER26 0xb1a
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#define CSR_MHPMCOUNTER27 0xb1b
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||||
#define CSR_MHPMCOUNTER28 0xb1c
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#define CSR_MHPMCOUNTER29 0xb1d
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#define CSR_MHPMCOUNTER30 0xb1e
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#define CSR_MHPMCOUNTER31 0xb1f
|
||||
#define CSR_MHPMEVENT3 0x323
|
||||
#define CSR_MHPMEVENT4 0x324
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#define CSR_MHPMEVENT5 0x325
|
||||
#define CSR_MHPMEVENT6 0x326
|
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#define CSR_MHPMEVENT7 0x327
|
||||
#define CSR_MHPMEVENT8 0x328
|
||||
#define CSR_MHPMEVENT9 0x329
|
||||
#define CSR_MHPMEVENT10 0x32a
|
||||
#define CSR_MHPMEVENT11 0x32b
|
||||
#define CSR_MHPMEVENT12 0x32c
|
||||
#define CSR_MHPMEVENT13 0x32d
|
||||
#define CSR_MHPMEVENT14 0x32e
|
||||
#define CSR_MHPMEVENT15 0x32f
|
||||
#define CSR_MHPMEVENT16 0x330
|
||||
#define CSR_MHPMEVENT17 0x331
|
||||
#define CSR_MHPMEVENT18 0x332
|
||||
#define CSR_MHPMEVENT19 0x333
|
||||
#define CSR_MHPMEVENT20 0x334
|
||||
#define CSR_MHPMEVENT21 0x335
|
||||
#define CSR_MHPMEVENT22 0x336
|
||||
#define CSR_MHPMEVENT23 0x337
|
||||
#define CSR_MHPMEVENT24 0x338
|
||||
#define CSR_MHPMEVENT25 0x339
|
||||
#define CSR_MHPMEVENT26 0x33a
|
||||
#define CSR_MHPMEVENT27 0x33b
|
||||
#define CSR_MHPMEVENT28 0x33c
|
||||
#define CSR_MHPMEVENT29 0x33d
|
||||
#define CSR_MHPMEVENT30 0x33e
|
||||
#define CSR_MHPMEVENT31 0x33f
|
||||
#define CSR_MVENDORID 0xf11
|
||||
#define CSR_MARCHID 0xf12
|
||||
#define CSR_MIMPID 0xf13
|
||||
#define CSR_MHARTID 0xf14
|
||||
#define CSR_CYCLEH 0xc80
|
||||
#define CSR_TIMEH 0xc81
|
||||
#define CSR_INSTRETH 0xc82
|
||||
#define CSR_HPMCOUNTER3H 0xc83
|
||||
#define CSR_HPMCOUNTER4H 0xc84
|
||||
#define CSR_HPMCOUNTER5H 0xc85
|
||||
#define CSR_HPMCOUNTER6H 0xc86
|
||||
#define CSR_HPMCOUNTER7H 0xc87
|
||||
#define CSR_HPMCOUNTER8H 0xc88
|
||||
#define CSR_HPMCOUNTER9H 0xc89
|
||||
#define CSR_HPMCOUNTER10H 0xc8a
|
||||
#define CSR_HPMCOUNTER11H 0xc8b
|
||||
#define CSR_HPMCOUNTER12H 0xc8c
|
||||
#define CSR_HPMCOUNTER13H 0xc8d
|
||||
#define CSR_HPMCOUNTER14H 0xc8e
|
||||
#define CSR_HPMCOUNTER15H 0xc8f
|
||||
#define CSR_HPMCOUNTER16H 0xc90
|
||||
#define CSR_HPMCOUNTER17H 0xc91
|
||||
#define CSR_HPMCOUNTER18H 0xc92
|
||||
#define CSR_HPMCOUNTER19H 0xc93
|
||||
#define CSR_HPMCOUNTER20H 0xc94
|
||||
#define CSR_HPMCOUNTER21H 0xc95
|
||||
#define CSR_HPMCOUNTER22H 0xc96
|
||||
#define CSR_HPMCOUNTER23H 0xc97
|
||||
#define CSR_HPMCOUNTER24H 0xc98
|
||||
#define CSR_HPMCOUNTER25H 0xc99
|
||||
#define CSR_HPMCOUNTER26H 0xc9a
|
||||
#define CSR_HPMCOUNTER27H 0xc9b
|
||||
#define CSR_HPMCOUNTER28H 0xc9c
|
||||
#define CSR_HPMCOUNTER29H 0xc9d
|
||||
#define CSR_HPMCOUNTER30H 0xc9e
|
||||
#define CSR_HPMCOUNTER31H 0xc9f
|
||||
#define CSR_MCYCLEH 0xb80
|
||||
#define CSR_MINSTRETH 0xb82
|
||||
#define CSR_MHPMCOUNTER3H 0xb83
|
||||
#define CSR_MHPMCOUNTER4H 0xb84
|
||||
#define CSR_MHPMCOUNTER5H 0xb85
|
||||
#define CSR_MHPMCOUNTER6H 0xb86
|
||||
#define CSR_MHPMCOUNTER7H 0xb87
|
||||
#define CSR_MHPMCOUNTER8H 0xb88
|
||||
#define CSR_MHPMCOUNTER9H 0xb89
|
||||
#define CSR_MHPMCOUNTER10H 0xb8a
|
||||
#define CSR_MHPMCOUNTER11H 0xb8b
|
||||
#define CSR_MHPMCOUNTER12H 0xb8c
|
||||
#define CSR_MHPMCOUNTER13H 0xb8d
|
||||
#define CSR_MHPMCOUNTER14H 0xb8e
|
||||
#define CSR_MHPMCOUNTER15H 0xb8f
|
||||
#define CSR_MHPMCOUNTER16H 0xb90
|
||||
#define CSR_MHPMCOUNTER17H 0xb91
|
||||
#define CSR_MHPMCOUNTER18H 0xb92
|
||||
#define CSR_MHPMCOUNTER19H 0xb93
|
||||
#define CSR_MHPMCOUNTER20H 0xb94
|
||||
#define CSR_MHPMCOUNTER21H 0xb95
|
||||
#define CSR_MHPMCOUNTER22H 0xb96
|
||||
#define CSR_MHPMCOUNTER23H 0xb97
|
||||
#define CSR_MHPMCOUNTER24H 0xb98
|
||||
#define CSR_MHPMCOUNTER25H 0xb99
|
||||
#define CSR_MHPMCOUNTER26H 0xb9a
|
||||
#define CSR_MHPMCOUNTER27H 0xb9b
|
||||
#define CSR_MHPMCOUNTER28H 0xb9c
|
||||
#define CSR_MHPMCOUNTER29H 0xb9d
|
||||
#define CSR_MHPMCOUNTER30H 0xb9e
|
||||
#define CSR_MHPMCOUNTER31H 0xb9f
|
||||
#define CSR_MENTROPY 0xF15
|
||||
#define CSR_MNOISE 0x7A9
|
||||
|
||||
#endif
|
||||
|
|
@ -246,6 +246,8 @@
|
|||
#define RVOPC_H3_BEXTMI_MASK 0b11100010000000000111000001111111
|
||||
|
||||
// C Extension
|
||||
#define RVOPC_ILLEGAL16_BITS 0b0000000000000000
|
||||
#define RVOPC_ILLEGAL16_MASK 0b1111111111111111
|
||||
#define RVOPC_C_ADDI4SPN_BITS 0b0000000000000000 // *** illegal if imm 0
|
||||
#define RVOPC_C_ADDI4SPN_MASK 0b1110000000000011
|
||||
#define RVOPC_C_LW_BITS 0b0100000000000000
|
||||
|
|
|
|||
|
|
@ -66,7 +66,9 @@ for test in testlist:
|
|||
|
||||
# Testbench itself should always exit successfully.
|
||||
if test_run_ret.returncode != 0:
|
||||
sys.exit("Negative return code from testbench!")
|
||||
print("Negative return code from testbench!")
|
||||
all_passed = False
|
||||
continue
|
||||
|
||||
# Pass if the program under test has zero exit code AND its output matches
|
||||
# the expected output (if there is an expected_output file)
|
||||
|
|
|
|||
Loading…
Reference in New Issue