Update to the latest riscv-arch-test. This uses the new test
framework -- scripts are a little janky for now. Note there is one test failure (cebreak-01) -- analysis shows this is due to the reference vector expecting mtval to be set informatively, whereas our implementation (legally) ties it to zero. Non-mtval-related signature for that test is correct so I'm saying this is fine.
This commit is contained in:
Luke Wren
parent
18d3b03cc8
commit
a861a110c1
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@ -1,9 +1,6 @@
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[submodule "test/riscv-compliance/riscv-compliance"]
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path = test/riscv-compliance/riscv-compliance
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url = https://github.com/riscv/riscv-compliance.git
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[submodule "test/sim/riscv-compliance/riscv-arch-test"]
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path = test/sim/riscv-compliance/riscv-arch-test
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url = https://github.com/riscv/riscv-arch-test.git
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url = https://github.com/wren6991/riscv-arch-test.git
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[submodule "scripts"]
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path = scripts
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url = https://github.com/Wren6991/fpgascripts
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@ -1,67 +0,0 @@
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TEST_ARCH = I
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BIN_ARCH = rv32i
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SIM_EXEC = ../tb_cxxrtl/tb
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CROSS_PREFIX = /opt/riscv/bin/riscv32-unknown-elf-
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TESTLIST= \
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add-01 \
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addi-01 \
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and-01 \
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andi-01 \
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auipc-01 \
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beq-01 \
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bge-01 \
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bgeu-01 \
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blt-01 \
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bltu-01 \
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bne-01 \
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fence-01 \
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jal-01 \
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jalr-01 \
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lb-align-01 \
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lbu-align-01 \
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lh-align-01 \
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lhu-align-01 \
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lui-01 \
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lw-align-01 \
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or-01 \
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ori-01 \
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sb-align-01 \
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sh-align-01 \
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sll-01 \
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slli-01 \
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slt-01 \
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slti-01 \
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sltiu-01 \
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sltu-01 \
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sra-01 \
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srai-01 \
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srl-01 \
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srli-01 \
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sub-01 \
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sw-align-01 \
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xor-01 \
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xori-01
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.PHONY: all testlist clean $(addprefix test-,$(TESTLIST))
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all: testlist
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define make-test-target
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# Turns out variable expansions inside functions don't work like I thought they did. Oh well this will do
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test-$1:
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mkdir -p tmp
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$(CROSS_PREFIX)gcc -I include -T memmap.ld -nostartfiles -march=$(BIN_ARCH) riscv-arch-test/riscv-test-suite/rv32i_m/$(TEST_ARCH)/src/$1.S -DXLEN=32 -o tmp/$(TEST_ARCH)-$1-on-$(BIN_ARCH).elf
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$(CROSS_PREFIX)objdump -h tmp/$(TEST_ARCH)-$1-on-$(BIN_ARCH).elf > tmp/$(TEST_ARCH)-$1-on-$(BIN_ARCH).dis
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$(CROSS_PREFIX)objdump -d tmp/$(TEST_ARCH)-$1-on-$(BIN_ARCH).elf >> tmp/$(TEST_ARCH)-$1-on-$(BIN_ARCH).dis
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$(CROSS_PREFIX)objcopy -O binary tmp/$(TEST_ARCH)-$1-on-$(BIN_ARCH).elf tmp/$(TEST_ARCH)-$1-on-$(BIN_ARCH).bin
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$(SIM_EXEC) --bin tmp/$(TEST_ARCH)-$1-on-$(BIN_ARCH).bin --vcd tmp/$(TEST_ARCH)-$1-on-$(BIN_ARCH).vcd --dump 0x400000 0x401000 --cycles 1000000 > tmp/$(TEST_ARCH)-$1-on-$(BIN_ARCH).log
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./compare_testvec tmp/$(TEST_ARCH)-$1-on-$(BIN_ARCH).log riscv-arch-test/riscv-test-suite/rv32i_m/$(TEST_ARCH)/references/$1.reference_output
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endef
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$(foreach test,$(TESTLIST),$(eval $(call make-test-target,$(test))))
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testlist: $(addprefix test-,$(TESTLIST))
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clean:
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rm -rf tmp/
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@ -0,0 +1,6 @@
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#!/bin/bash
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set -e
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make -C riscv-arch-test RISCV_TARGET=hazard3 RISCV_DEVICE=I clean
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make -C riscv-arch-test RISCV_TARGET=hazard3 RISCV_DEVICE=M clean
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make -C riscv-arch-test RISCV_TARGET=hazard3 RISCV_DEVICE=C clean
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@ -1 +0,0 @@
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../riscv-arch-test/riscv-test-env/arch_test.h
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@ -1 +0,0 @@
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../riscv-arch-test/riscv-test-env/encoding.h
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@ -1,102 +0,0 @@
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#ifndef _COMPLIANCE_MODEL_H
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#define _COMPLIANCE_MODEL_H
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// Modified version of riscv-arch-test/riscv-target/example-target/model_test.h
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#define IO_BASE 0x80000000
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#define IO_PRINT_CHAR (IO_BASE + 0x0)
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#define IO_PRINT_U32 (IO_BASE + 0x4)
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#define IO_EXIT (IO_BASE + 0x8)
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#define RVMODEL_DATA_SECTION \
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.pushsection .testdata,"aw",@progbits; \
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.align 8; .global tohost; tohost: .dword 0; \
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.align 8; .global fromhost; fromhost: .dword 0; \
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.popsection; \
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.align 8; .global begin_regstate; begin_regstate: \
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.word 128; \
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.align 8; .global end_regstate; end_regstate: \
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.word 4;
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#define RVMODEL_HALT ; \
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li a0, IO_EXIT ; \
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li a1, 0 ; \
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sw a1, (a0) ; \
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1: j 1b \
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//TODO: declare the start of your signature region here. Nothing else to be used here.
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// The .align 4 ensures that the signature ends at a 16-byte boundary
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#define RVMODEL_DATA_BEGIN \
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.section .testdata, "aw"; \
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.align 4; .global begin_signature; begin_signature:
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//TODO: declare the end of the signature region here. Add other target specific contents here.
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#define RVMODEL_DATA_END \
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.align 4; .global end_signature; end_signature: \
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RVMODEL_DATA_SECTION
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#define RVMODEL_BOOT
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// _SP = (volatile register)
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//TODO: Macro to output a string to IO
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#define LOCAL_IO_WRITE_STR(_STR) RVMODEL_IO_WRITE_STR(x31, _STR)
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// Shut up
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#define RVMODEL_IO_WRITE_STR(_STR, ...)
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// #define RVMODEL_IO_WRITE_STR(_SP, _STR) \
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// .section .data.string; \
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// 20001: \
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// .string _STR; \
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// .section .text.init; \
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// la a0, 20001b; \
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// jal FN_WriteStr;
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#define RSIZE 4
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// _SP = (volatile register)
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#define LOCAL_IO_PUSH(_SP) \
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la _SP, begin_regstate; \
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sw ra, (1*RSIZE)(_SP); \
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sw t0, (2*RSIZE)(_SP); \
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sw t1, (3*RSIZE)(_SP); \
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sw t2, (4*RSIZE)(_SP); \
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sw t3, (5*RSIZE)(_SP); \
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sw t4, (6*RSIZE)(_SP); \
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sw s0, (7*RSIZE)(_SP); \
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sw a0, (8*RSIZE)(_SP);
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// _SP = (volatile register)
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#define LOCAL_IO_POP(_SP) \
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la _SP, begin_regstate; \
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lw ra, (1*RSIZE)(_SP); \
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lw t0, (2*RSIZE)(_SP); \
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lw t1, (3*RSIZE)(_SP); \
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lw t2, (4*RSIZE)(_SP); \
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lw t3, (5*RSIZE)(_SP); \
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lw t4, (6*RSIZE)(_SP); \
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lw s0, (7*RSIZE)(_SP); \
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lw a0, (8*RSIZE)(_SP);
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#define RVMODEL_IO_ASSERT_GPR_EQ(_SP, _R, _I)
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//RVTEST_IO_ASSERT_SFPR_EQ
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#define RVMODEL_IO_ASSERT_SFPR_EQ(_F, _R, _I)
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//RVTEST_IO_ASSERT_DFPR_EQ
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#define RVMODEL_IO_ASSERT_DFPR_EQ(_D, _R, _I)
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// TODO: specify the routine for setting machine software interrupt
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#define RVMODEL_SET_MSW_INT
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// TODO: specify the routine for clearing machine software interrupt
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#define RVMODEL_CLEAR_MSW_INT
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// TODO: specify the routine for clearing machine timer interrupt
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#define RVMODEL_CLEAR_MTIMER_INT
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// TODO: specify the routine for clearing machine external interrupt
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#define RVMODEL_CLEAR_MEXT_INT
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#endif // _COMPLIANCE_MODEL_H
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@ -1,41 +0,0 @@
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MEMORY
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{
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RAM (wx) : ORIGIN = 0x0, LENGTH = 4M
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RESULT (w) : ORIGIN = ORIGIN(RAM) + LENGTH(RAM), LENGTH = 64k
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}
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OUTPUT_FORMAT("elf32-littleriscv", "elf32-littleriscv", "elf32-littleriscv")
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OUTPUT_ARCH(riscv)
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ENTRY(_start)
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SECTIONS
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{
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.text : {
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. = ORIGIN(RAM) + 0x40;
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PROVIDE (_start = .);
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*(.text*)
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. = ALIGN(4);
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} > RAM
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.rodata : {
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*(.rodata*)
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. = ALIGN(4);
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} > RAM
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.data : {
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*(.data*)
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. = ALIGN(4);
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} > RAM
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.bss : {
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*(.bss .bss.*)
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. = ALIGN(4);
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} > RAM
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/* Link testout section to upper memory region */
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.testdata :
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{
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PROVIDE(__testdata_start = .);
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*(.testdata)
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} > RESULT
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}
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@ -1 +1 @@
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Subproject commit b436dd0939c968f2c3da86bb9b63bb2dfe03b134
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Subproject commit 759666d875dfebd8a5f62134dfb8b70f801d897d
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@ -1,4 +1,4 @@
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#!/bin/bash
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set -e
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set -ex
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make
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make -C riscv-arch-test RISCV_TARGET=hazard3 RISCV_DEVICE=I
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@ -1,32 +1,15 @@
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#!/bin/bash
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set -e
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make TEST_ARCH=C BIN_ARCH=rv32ic TESTLIST=" \
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cadd-01 \
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caddi16sp-01 \
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cand-01 \
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cbeqz-01 \
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cjal-01 \
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cjr-01 \
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clui-01 \
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clwsp-01 \
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cnop-01 \
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cslli-01 \
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csrli-01 \
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csw-01 \
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cxor-01 \
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caddi-01 \
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caddi4spn-01 \
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candi-01 \
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cbnez-01 \
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cj-01 \
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cjalr-01 \
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cli-01 \
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clw-01 \
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cmv-01 \
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cor-01 \
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csrai-01 \
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csub-01 \
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cswsp-01 \
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"
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#cebreak-01 \
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# Note c.ebreak is expected to fail due to not correctly handling mtval being
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# (legally) hardwired to 0.
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# Not clear yet whether this is a configuration issue or an issue with the
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# reference vector generation/selection, but I've debugged the test, and the
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# non-mtval-related parts of the signature are good.
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make -C riscv-arch-test RISCV_TARGET=hazard3 RISCV_DEVICE=C || echo "
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Note cebreak-01 is an expected failure: test does not correctly handle hardwired mtval.
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If you see any other failures, that is a cause for concern."
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@ -1,13 +1,4 @@
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#!/bin/bash
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set -e
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make TEST_ARCH=M BIN_ARCH=rv32imc TESTLIST=" \
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div-01 \
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divu-01 \
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rem-01 \
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remu-01 \
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mul-01 \
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mulhu-01 \
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mulh-01 \
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mulhsu-01 \
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"
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make -C riscv-arch-test RISCV_TARGET=hazard3 RISCV_DEVICE=I
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@ -4,5 +4,3 @@ set -e
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./run_32i.sh
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./run_32im.sh
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./run_32ic.sh
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# These are TODO for sw reasons -- not sure why they don't bundle the handlers with the tests
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# ./run_32privilege.sh
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@ -0,0 +1,42 @@
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#!/usr/bin/env python3
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import sys
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import os
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model = []
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log_path = sys.argv[1] + ".stdout"
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elf_path = sys.argv[1] + ".elf"
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sigout_path = sys.argv[2]
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model_bytes = []
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in_testdata = False
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for l in open(log_path):
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if l.startswith("Dumping memory"):
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in_testdata = True
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continue
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if in_testdata:
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try:
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model_bytes.extend(int(x, 16) for x in l.split(" "))
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except ValueError:
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break
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for i in range(len(model_bytes) // 4):
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model.append(model_bytes[i * 4] | model_bytes[i * 4 + 1] << 8 | model_bytes[i * 4 + 2] << 16 | model_bytes[i * 4 + 3] << 24)
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# Trim the output down to size before writing out, by scraping the symbols out
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# of the ELF. New riscv-compliance comparison script doesn't accept trailing data.
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# Assume that a suitable objdump is on PATH -- sorry, I couldn't figure out
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# what on earth they were trying to do with the target creation in their
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# Makefile fragments, so it's just been hacked into this script. Problem for
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# future Luke
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sig_start_addr = int(os.popen("riscv32-unknown-elf-objdump -t " + elf_path + " | grep begin_signature | head -c8").read(), 16)
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sig_end_addr = int(os.popen("riscv32-unknown-elf-objdump -t " + elf_path + " | grep end_signature | head -c8").read(), 16)
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sig_size_words = (sig_end_addr - sig_start_addr) // 4
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model = model[:sig_size_words]
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ofile = open(sigout_path, "w")
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for n in model:
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ofile.write(f"{n:08x}\n")
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Loading…
Reference in New Issue