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Refine soc_cxxrtl and pass demo.

This commit is contained in:
Colin 2025-03-27 15:49:16 +08:00
parent 616da81d63
commit 5ec810907e
6 changed files with 83 additions and 72 deletions
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1
.gitignore vendored
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@ -1,2 +1,3 @@
.DS_Store
*.todo
.vscode

2
test/sim/common/src_only_app.mk
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@ -9,7 +9,7 @@ endif
DOTF ?= tb.f
CCFLAGS ?=
LDSCRIPT ?= ../common/memmap.ld
CROSS_PREFIX ?= riscv32-unknown-elf-
CROSS_PREFIX ?= /opt/riscv/bin/riscv32-unknown-elf-
TBEXEC ?= ../tb_cxxrtl/tb
TBDIR := $(dir $(abspath $(TBEXEC)))
INCDIR ?= ../common

2
test/sim/common/tb_cxxrtl_io.h
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@ -9,7 +9,7 @@
// ----------------------------------------------------------------------------
// Testbench IO hardware layout
#define IO_BASE 0x80000000
#define IO_BASE 0x40000000
typedef struct {
volatile uint32_t print_char;

11
test/sim/soc_cxxrtl/Makefile
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@ -3,7 +3,7 @@
include ../project_paths.mk
TOP := tb
TOP := example_soc
DOTF := tb.f
CONFIG := default
TBEXEC := $(patsubst %.f,%,$(DOTF))
@ -30,6 +30,15 @@ $(BUILD_DIR)/dut.cpp: $(FILE_LIST) $(wildcard *.vh)
clean::
rm -rf $(BUILD_DIR) $(TBEXEC)
sim: $(TBEXEC)
./$(TBEXEC) --port 9824
openocd:
openocd -f openocd.cfg
gdb:
/opt/riscv/bin/riscv32-unknown-elf-gdb -x gdb_init
$(TBEXEC): $(BUILD_DIR)/dut.cpp tb.cpp
$(CLANGXX) -O3 -std=c++14 $(addprefix -D,$(CDEFINES) $(CDEFINES_$(DOTF))) -I $(shell yosys-config --datdir)/include/backends/cxxrtl/runtime -I $(BUILD_DIR) tb.cpp -o $(TBEXEC)

136
test/sim/soc_cxxrtl/tb.cpp
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@ -74,10 +74,10 @@ struct mem_io_state {
// Where we're going we don't need a destructor B-)
void step(cxxrtl_design::p_tb &tb) {
void step(cxxrtl_design::p_example__soc &tb) {
// Default update logic for mtime, mtimecmp
++mtime;
tb.p_timer__irq.set<uint8_t>((mtime >= mtimecmp[0]) | (mtime >= mtimecmp[1]) << 1);
// tb.p_timer__irq.set<uint8_t>((mtime >= mtimecmp[0]) | (mtime >= mtimecmp[1]) << 1);
}
};
@ -105,7 +105,7 @@ struct bus_response {
bus_response(): rdata(0), stall_cycles(0), err(false), exokay(true) {}
};
bus_response mem_access(cxxrtl_design::p_tb &tb, mem_io_state &memio, bus_request req) {
bus_response mem_access(cxxrtl_design::p_example__soc &tb, mem_io_state &memio, bus_request req) {
bus_response resp;
// Global monitor. When monitor is not enabled, HEXOKAY is tied high
@ -171,19 +171,19 @@ bus_response mem_access(cxxrtl_design::p_tb &tb, mem_io_state &memio, bus_reques
}
}
else if (req.addr == IO_BASE + IO_SET_SOFTIRQ) {
tb.p_soft__irq.set<uint8_t>(tb.p_soft__irq.get<uint8_t>() | req.wdata);
// tb.p_soft__irq.set<uint8_t>(tb.p_soft__irq.get<uint8_t>() | req.wdata);
}
else if (req.addr == IO_BASE + IO_CLR_SOFTIRQ) {
tb.p_soft__irq.set<uint8_t>(tb.p_soft__irq.get<uint8_t>() & ~req.wdata);
// tb.p_soft__irq.set<uint8_t>(tb.p_soft__irq.get<uint8_t>() & ~req.wdata);
}
else if (req.addr == IO_BASE + IO_GLOBMON_EN) {
memio.monitor_enabled = req.wdata;
}
else if (req.addr == IO_BASE + IO_SET_IRQ) {
tb.p_irq.set<uint32_t>(tb.p_irq.get<uint32_t>() | req.wdata);
// tb.p_irq.set<uint32_t>(tb.p_irq.get<uint32_t>() | req.wdata);
}
else if (req.addr == IO_BASE + IO_CLR_IRQ) {
tb.p_irq.set<uint32_t>(tb.p_irq.get<uint32_t>() & ~req.wdata);
// tb.p_irq.set<uint32_t>(tb.p_irq.get<uint32_t>() & ~req.wdata);
}
else if (req.addr == IO_BASE + IO_MTIME) {
memio.mtime = (memio.mtime & 0xffffffff00000000u) | req.wdata;
@ -217,10 +217,10 @@ bus_response mem_access(cxxrtl_design::p_tb &tb, mem_io_state &memio, bus_reques
memio.mem[req.addr + 3] << 24;
}
else if (req.addr == IO_BASE + IO_SET_SOFTIRQ || req.addr == IO_BASE + IO_CLR_SOFTIRQ) {
resp.rdata = tb.p_soft__irq.get<uint8_t>();
// resp.rdata = tb.p_soft__irq.get<uint8_t>();
}
else if (req.addr == IO_BASE + IO_SET_IRQ || req.addr == IO_BASE + IO_CLR_IRQ) {
resp.rdata = tb.p_irq.get<uint32_t>();
// resp.rdata = tb.p_irq.get<uint32_t>();
}
else if (req.addr == IO_BASE + IO_MTIME) {
resp.rdata = memio.mtime;
@ -449,7 +449,7 @@ int main(int argc, char **argv) {
}
}
cxxrtl_design::p_tb top;
cxxrtl_design::p_example__soc top;
std::ofstream waves_fd;
cxxrtl::vcd_writer vcd;
@ -470,8 +470,8 @@ int main(int argc, char **argv) {
req_d.reservation_id = 1;
// Set bus interfaces to generate good IDLE responses at first
top.p_i__hready.set<bool>(true);
top.p_d__hready.set<bool>(true);
// top.p_i__hready.set<bool>(true);
// top.p_d__hready.set<bool>(true);
// Reset + initial clock pulse
@ -580,68 +580,68 @@ int main(int argc, char **argv) {
// - A single, single-ported processor (instruction fetch + load/store muxed internally)
// - A pair of single-ported processors, for dual-core debug tests
if (top.p_d__hready.get<bool>()) {
// Clear bus error by default
top.p_d__hresp.set<bool>(false);
// if (top.p_d__hready.get<bool>()) {
// // Clear bus error by default
// top.p_d__hresp.set<bool>(false);
// Handle current data phase
req_d.wdata = top.p_d__hwdata.get<uint32_t>();
bus_response resp;
if (req_d_vld)
resp = mem_access(top, memio, req_d);
else
resp.exokay = !memio.monitor_enabled;
if (resp.err) {
// Phase 1 of error response
top.p_d__hready.set<bool>(false);
top.p_d__hresp.set<bool>(true);
}
top.p_d__hrdata.set<uint32_t>(resp.rdata);
top.p_d__hexokay.set<bool>(resp.exokay);
// // Handle current data phase
// req_d.wdata = top.p_d__hwdata.get<uint32_t>();
// bus_response resp;
// if (req_d_vld)
// resp = mem_access(top, memio, req_d);
// else
// resp.exokay = !memio.monitor_enabled;
// if (resp.err) {
// // Phase 1 of error response
// top.p_d__hready.set<bool>(false);
// top.p_d__hresp.set<bool>(true);
// }
// top.p_d__hrdata.set<uint32_t>(resp.rdata);
// top.p_d__hexokay.set<bool>(resp.exokay);
// Progress current address phase to data phase
req_d_vld = top.p_d__htrans.get<uint8_t>() >> 1;
req_d.write = top.p_d__hwrite.get<bool>();
req_d.size = (bus_size_t)top.p_d__hsize.get<uint8_t>();
req_d.addr = top.p_d__haddr.get<uint32_t>();
req_d.excl = top.p_d__hexcl.get<bool>();
}
else {
// hready=0. Currently this only happens when we're in the first
// phase of an error response, so go to phase 2.
top.p_d__hready.set<bool>(true);
}
// // Progress current address phase to data phase
// req_d_vld = top.p_d__htrans.get<uint8_t>() >> 1;
// req_d.write = top.p_d__hwrite.get<bool>();
// req_d.size = (bus_size_t)top.p_d__hsize.get<uint8_t>();
// req_d.addr = top.p_d__haddr.get<uint32_t>();
// req_d.excl = top.p_d__hexcl.get<bool>();
// }
// else {
// // hready=0. Currently this only happens when we're in the first
// // phase of an error response, so go to phase 2.
// top.p_d__hready.set<bool>(true);
// }
if (top.p_i__hready.get<bool>()) {
top.p_i__hresp.set<bool>(false);
// if (top.p_i__hready.get<bool>()) {
// top.p_i__hresp.set<bool>(false);
req_i.wdata = top.p_i__hwdata.get<uint32_t>();
bus_response resp;
if (req_i_vld)
resp = mem_access(top, memio, req_i);
else
resp.exokay = !memio.monitor_enabled;
if (resp.err) {
// Phase 1 of error response
top.p_i__hready.set<bool>(false);
top.p_i__hresp.set<bool>(true);
}
top.p_i__hrdata.set<uint32_t>(resp.rdata);
top.p_i__hexokay.set<bool>(resp.exokay);
// req_i.wdata = top.p_i__hwdata.get<uint32_t>();
// bus_response resp;
// if (req_i_vld)
// resp = mem_access(top, memio, req_i);
// else
// resp.exokay = !memio.monitor_enabled;
// if (resp.err) {
// // Phase 1 of error response
// top.p_i__hready.set<bool>(false);
// top.p_i__hresp.set<bool>(true);
// }
// top.p_i__hrdata.set<uint32_t>(resp.rdata);
// top.p_i__hexokay.set<bool>(resp.exokay);
// Progress current address phase to data phase
req_i_vld = top.p_i__htrans.get<uint8_t>() >> 1;
req_i.write = top.p_i__hwrite.get<bool>();
req_i.size = (bus_size_t)top.p_i__hsize.get<uint8_t>();
req_i.addr = top.p_i__haddr.get<uint32_t>();
req_i.excl = top.p_i__hexcl.get<bool>();
}
else {
// hready=0. Currently this only happens when we're in the first
// phase of an error response, so go to phase 2.
top.p_i__hready.set<bool>(true);
}
// // Progress current address phase to data phase
// req_i_vld = top.p_i__htrans.get<uint8_t>() >> 1;
// req_i.write = top.p_i__hwrite.get<bool>();
// req_i.size = (bus_size_t)top.p_i__hsize.get<uint8_t>();
// req_i.addr = top.p_i__haddr.get<uint32_t>();
// req_i.excl = top.p_i__hexcl.get<bool>();
// }
// else {
// // hready=0. Currently this only happens when we're in the first
// // phase of an error response, so go to phase 2.
// top.p_i__hready.set<bool>(true);
// }
if (dump_waves) {
// The extra step() is just here to get the bus responses to line up nicely

3
test/sim/soc_cxxrtl/tb.f
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@ -1,2 +1,3 @@
file tb.v
list $HDL/../example_soc/soc/soc.f
file $HDL/debug/cdc/hazard3_reset_sync.v
list tb_common.f