Remove external IRQ vectors from init.S which are unreachable now that midcr.eivect has been removed.
This commit is contained in:
Luke Wren
parent
607147f280
commit
c5d6be24f3
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@ -17,6 +17,7 @@
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.macro VEC name:req
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.p2align 2
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j \name
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.p2align 2
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.endm
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// ----------------------------------------------------------------------------
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@ -49,46 +50,10 @@ j \name
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VEC .halt
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VEC .halt
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// When midcr.eivect is 1, hardware vectors IRQs directly to the
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// platform-specific part of the vector table. Otherwise, software indexes
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// this table in the prologue of a shared external IRQ handler.
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.p2align 2
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platform_vectors:
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VEC isr_irq0
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VEC isr_irq1
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VEC isr_irq2
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VEC isr_irq3
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VEC isr_irq4
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VEC isr_irq5
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VEC isr_irq6
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VEC isr_irq7
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VEC isr_irq8
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VEC isr_irq9
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VEC isr_irq10
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VEC isr_irq11
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VEC isr_irq12
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VEC isr_irq13
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VEC isr_irq14
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VEC isr_irq15
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VEC isr_irq16
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VEC isr_irq17
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VEC isr_irq18
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VEC isr_irq19
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VEC isr_irq20
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VEC isr_irq21
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VEC isr_irq22
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VEC isr_irq23
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VEC isr_irq24
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VEC isr_irq25
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VEC isr_irq26
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VEC isr_irq27
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VEC isr_irq28
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VEC isr_irq29
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VEC isr_irq30
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VEC isr_irq31
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// TODO remove (update ldscripts first)
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.rept 32
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.word 0
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.endr
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// ----------------------------------------------------------------------------
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// Reset handler
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@ -133,92 +98,7 @@ heap_ptr:
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j .halt
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progname:
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.asciz "hazard5-testbench"
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// ----------------------------------------------------------------------------
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// Soft external IRQ dispatch
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// Vector isr_external_irq to the relevant ISR, based on mcause. The ISR can
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// be a standard C-ABI function. This method also leaves the possibility of
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// using addresses in the IRQ vector table, rather than jump instructions.
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.global isr_external_irq
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.weak isr_external_irq
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isr_external_irq:
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// Save all caller-saves, plus three callee saves for CSR saving
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addi sp, sp, -80
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sw ra, 0(sp)
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sw t0, 4(sp)
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sw t1, 8(sp)
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sw t2, 12(sp)
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sw t3, 16(sp)
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sw t4, 20(sp)
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sw t5, 24(sp)
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sw t6, 28(sp)
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sw a0, 32(sp)
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sw a1, 36(sp)
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sw a2, 40(sp)
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sw a3, 44(sp)
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sw a4, 48(sp)
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sw a5, 52(sp)
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sw a6, 56(sp)
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sw a7, 60(sp)
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sw s0, 64(sp)
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sw s1, 68(sp)
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sw s2, 72(sp)
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// Save exception state to callee-saves so we can use it for return
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csrr s0, mepc
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csrr s1, mstatus
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csrr s2, hazard3_csr_meie0
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// Calculate IRQ entry point
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csrr a0, mcause
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slli a0, a0, 2
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csrr a1, mtvec
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andi a1, a1, -4
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add a1, a1, a0
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// Mask off higher-numbered IRQs (and this IRQ), then re-enable IRQs so we
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// can be preempted. Could have some other priority scheme here.
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srli a0, a0, 2
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addi a0, a0, -16
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li a2, -1
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sll a2, a2, a0
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csrc hazard3_csr_meie0, a2
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csrsi mstatus, 8
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// Enter IRQ
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jalr a1
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trap_return:
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// No more preemption until we mret.
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csrci mstatus, 8
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csrw mepc, s0
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csrw mstatus, s1
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csrw hazard3_csr_meie0, s2
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lw ra, 0(sp)
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lw t0, 4(sp)
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lw t1, 8(sp)
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lw t2, 12(sp)
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lw t3, 16(sp)
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lw t4, 20(sp)
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lw t5, 24(sp)
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lw t6, 28(sp)
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lw a0, 32(sp)
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lw a1, 36(sp)
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lw a2, 40(sp)
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lw a3, 44(sp)
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lw a4, 48(sp)
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lw a5, 52(sp)
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lw a6, 56(sp)
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lw a7, 60(sp)
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lw s0, 64(sp)
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lw s1, 68(sp)
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lw s2, 72(sp)
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addi sp, sp, 80
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mret
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.asciz "hazard3-testbench"
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// ----------------------------------------------------------------------------
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// Weak handler/ISR symbols
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@ -307,38 +187,7 @@ _str_\name:
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weak_handler handle_exception
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weak_handler isr_machine_softirq
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weak_handler isr_machine_timer
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weak_handler isr_irq0
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weak_handler isr_irq1
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weak_handler isr_irq2
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weak_handler isr_irq3
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weak_handler isr_irq4
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weak_handler isr_irq5
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weak_handler isr_irq6
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weak_handler isr_irq7
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weak_handler isr_irq8
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weak_handler isr_irq9
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weak_handler isr_irq10
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weak_handler isr_irq11
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weak_handler isr_irq12
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weak_handler isr_irq13
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weak_handler isr_irq14
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weak_handler isr_irq15
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weak_handler isr_irq16
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weak_handler isr_irq17
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weak_handler isr_irq18
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weak_handler isr_irq19
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weak_handler isr_irq20
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weak_handler isr_irq21
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weak_handler isr_irq22
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weak_handler isr_irq23
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weak_handler isr_irq24
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weak_handler isr_irq25
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weak_handler isr_irq26
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weak_handler isr_irq27
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weak_handler isr_irq28
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weak_handler isr_irq29
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weak_handler isr_irq30
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weak_handler isr_irq31
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weak_handler isr_external_irq
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// You can relax now
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.option pop
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