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Fix some issues in predecode of register numbers for compressed ISA. RV32IC compliance now passes, hello world does not work still

This commit is contained in:
Luke Wren 2021-05-22 10:16:02 +01:00
parent 692abbad8b
commit cc6f590f2e
5 changed files with 12 additions and 4 deletions
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10
hdl/hazard3_frontend.v
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@ -304,8 +304,14 @@ wire next_instr_is_32bit = next_instr[1:0] == 2'b11;
assign next_regs_vld = next_instr_is_32bit ? buf_level_next[1] : |buf_level_next;
assign next_regs_rs1 =
next_instr_is_32bit ? next_instr[19:15] :
next_instr[1:0] == 2'b10 ? next_instr[11:7] : {2'b01, next_instr[9:7]};
next_instr_is_32bit ? next_instr[19:15] : // 32-bit R, S, B formats
next_instr[1:0] == 2'b00 && next_instr[15:13] == 3'b000 ? 5'd2 : // c.addi4spn
next_instr[1:0] == 2'b01 && next_instr[15:13] == 3'b011 ? 5'd2 : // c.addi16sp
next_instr[1:0] == 2'b10 && next_instr[15:13] == 3'b010 ? 5'd2 : // c.lwsp
next_instr[1:0] == 2'b10 && next_instr[15:13] == 3'b110 ? 5'd2 : // c.swsp
next_instr[1:0] == 2'b01 && next_instr[15:13] == 3'b000 ? next_instr[11:7] : // c.addi
next_instr[1:0] == 2'b10 ? next_instr[11:7] :
{2'b01, next_instr[9:7]};
assign next_regs_rs2 =
next_instr_is_32bit ? next_instr[24:20] :

2
test/dhrystone/Makefile
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@ -1,6 +1,6 @@
SRCS := ../common/init.S src/dhrystone_main.c src/dhrystone.c src/util.c
APP := dhrystone
CCFLAGS := -O3 -fno-inline
CCFLAGS := -O3 -fno-inline -march=rv32i
MAX_CYCLES := 1000000
include ../common/src_only_app.mk

1
test/hellow/Makefile
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@ -1,4 +1,5 @@
SRCS := ../common/init.S main.c
APP := hellow
CCFLAGS = -march=rv32ic
include ../common/src_only_app.mk

2
test/riscv-compliance/include/model_test.h
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@ -44,7 +44,7 @@
#define LOCAL_IO_WRITE_STR(_STR) RVMODEL_IO_WRITE_STR(x31, _STR)
// Shut up
#define RVMODEL_IO_WRITE_STR(_STR)
#define RVMODEL_IO_WRITE_STR(_STR, ...)
// #define RVMODEL_IO_WRITE_STR(_SP, _STR) \
// .section .data.string; \

1
test/riscv-compliance/memmap.ld
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@ -11,6 +11,7 @@ ENTRY(_start)
SECTIONS
{
.text : {
. = ORIGIN(RAM) + 0xc0;
PROVIDE (_start = .);
*(.text*)
. = ALIGN(4);