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Beef up the ULX3S SoC again now that atomics aren't so disastrous for timing

This commit is contained in:
Luke Wren 2021-12-18 02:41:50 +00:00
parent 6b8d4913ee
commit d1b5f83b7a
1 changed files with 2 additions and 2 deletions
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4
example_soc/fpga/fpga_ulx3s.v
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@ -33,7 +33,7 @@ fpga_reset #(
example_soc #(
.DTM_TYPE ("ECP5"),
.SRAM_DEPTH (1 << 12),
.SRAM_DEPTH (1 << 15),
.EXTENSION_M (1),
.EXTENSION_A (1),
@ -43,7 +43,7 @@ example_soc #(
.EXTENSION_ZBC (0),
.EXTENSION_ZBS (0),
.CSR_COUNTER (0),
.MUL_FAST (0),
.MUL_FAST (1),
.MULDIV_UNROLL (1)
) soc_u (
.clk (clk_sys),