Arrange for address buses to be 0 when processor is held in reset

hdl/hazard3_decode.v

@@ -359,6 +359,9 @@ always @ (*) begin
 		d_sleep_wfi       = 1'b0;
 		d_sleep_block     = 1'b0;
 		d_sleep_unblock   = 1'b0;
+		// Ensure address bus is 0 in reset if register file is resettable:
+		d_addr_is_regoffs = 1'b1;
+
 		if (EXTENSION_M)
 			d_aluop = ALUOP_ADD;
 

hdl/hazard3_frontend.v

@@ -312,7 +312,7 @@ always @ (*) begin
 	mem_addr_vld_r = 1'b1;
 	case (1'b1)
 		mem_addr_hold                    : begin mem_addr_r = fetch_addr; end
-		jump_target_vld             : begin
+		jump_target_vld || reset_holdoff : begin
 		                                         mem_addr_r = {jump_target[W_ADDR-1:2], 2'b00};
 		                                         mem_priv_r = jump_priv || !U_MODE;
 		end