Fix bad handshake on bus error response (need to report both phases of response, to get clean exception entry

hdl/hazard3_cpu_1port.v

@@ -231,8 +231,11 @@ assign core_aph_ready_i = ahblm_hready && bus_gnt_i;
 assign core_dph_ready_i = ahblm_hready && bus_active_dph_i;
 assign core_dph_err_i   = ahblm_hready && bus_active_dph_i && ahblm_hresp;
 
+// D-side errors are reported even when not ready, so that the core can make
+// use of the two-phase error response to cleanly squash a second load/store
+// chasing the faulting one down the pipeline.
 assign core_aph_ready_d = ahblm_hready && bus_gnt_d;
 assign core_dph_ready_d = ahblm_hready && bus_active_dph_d;
-assign core_dph_err_d   = ahblm_hready && bus_active_dph_d && ahblm_hresp;
+assign core_dph_err_d = bus_active_dph_d && ahblm_hresp;
 
 endmodule

hdl/hazard3_cpu_2port.v

@@ -199,9 +199,12 @@ always @ (posedge clk or negedge rst_n)
 	else if (d_hready)
 		dphase_active_d <= core_aph_req_d;
 
+// D-side errors are reported even when not ready, so that the core can make
+// use of the two-phase error response to cleanly squash a second load/store
+// chasing the faulting one down the pipeline.
 assign core_aph_ready_d = d_hready && core_aph_req_d;
 assign core_dph_ready_d = d_hready && dphase_active_d;
-assign core_dph_err_d   = d_hready && dphase_active_d && d_hresp;
+assign core_dph_err_d = dphase_active_d && d_hresp;
 
 assign core_rdata_d = d_hrdata;
 assign d_hwdata = core_wdata_d;