colin
/
Hazard3
1
0
Fork 0
Code Issues Pull Requests Packages Projects Releases Wiki Activity

Remove unused FAKE_DUALPORT option from regfile

This commit is contained in:
Luke Wren 2022-05-23 16:22:01 +01:00
parent f849517202
commit da244f54c3
1 changed files with 1 additions and 19 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

20
hdl/hazard3_regfile_1w2r.v
View File

@ -6,15 +6,9 @@
// Register file // Register file
// Single write port, dual read port // Single write port, dual read port
// FAKE_DUALPORT: if 1, implement regfile with pair of memories.
// Write ports are ganged together, read ports operate independently.
// This allows BRAM inference on FPGAs with single-read-port BRAMs.
// (Looking at you iCE40)
`default_nettype none `default_nettype none
module hazard3_regfile_1w2r #( module hazard3_regfile_1w2r #(
parameter FAKE_DUALPORT = 0,
parameter RESET_REGS = 0, // Unsupported for FAKE_DUALPORT parameter RESET_REGS = 0, // Unsupported for FAKE_DUALPORT
parameter N_REGS = 16, parameter N_REGS = 16,
parameter W_DATA = 32, parameter W_DATA = 32,
@ -35,19 +29,7 @@ module hazard3_regfile_1w2r #(
); );
generate generate
if (FAKE_DUALPORT) begin: fake_dualport if (RESET_REGS) begin: real_dualport_reset
reg [W_DATA-1:0] mem1 [0:N_REGS-1];
reg [W_DATA-1:0] mem2 [0:N_REGS-1];
always @ (posedge clk) begin
if (wen) begin
mem1[waddr] <= wdata;
mem2[waddr] <= wdata;
end
rdata1 <= mem1[raddr1];
rdata2 <= mem2[raddr2];
end
end else if (RESET_REGS) begin: real_dualport_reset
// This will presumably always be implemented with flops // This will presumably always be implemented with flops
reg [W_DATA-1:0] mem [0:N_REGS-1]; reg [W_DATA-1:0] mem [0:N_REGS-1];