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Fix exception being passed to M when X is stalled but M is not (a load which had an unaligned address spuriously during a RAW stall on the result register)

This commit is contained in:
Luke Wren 2021-05-29 22:52:50 +01:00
parent 4b9a3c2c78
commit ea5db61582
1 changed files with 1 additions and 1 deletions
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2
hdl/hazard3_core.v
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@ -516,13 +516,13 @@ always @ (posedge clk or negedge rst_n) begin
{xm_rs1, xm_rs2, xm_rd} <= {d_rs1, d_rs2, d_rd}; {xm_rs1, xm_rs2, xm_rd} <= {d_rs1, d_rs2, d_rd};
// If the transfer is unaligned, make sure it is completely NOP'd on the bus // If the transfer is unaligned, make sure it is completely NOP'd on the bus
xm_memop <= d_memop | {x_unaligned_addr, 3'h0}; xm_memop <= d_memop | {x_unaligned_addr, 3'h0};
xm_except <= x_except;
if (x_stall || m_trap_enter_vld) begin if (x_stall || m_trap_enter_vld) begin
// Insert bubble // Insert bubble
xm_rd <= {W_REGADDR{1'b0}}; xm_rd <= {W_REGADDR{1'b0}};
xm_memop <= MEMOP_NONE; xm_memop <= MEMOP_NONE;
xm_except <= EXCEPT_NONE; xm_except <= EXCEPT_NONE;
end end
xm_except <= x_except;
end else if (bus_dph_err_d) begin end else if (bus_dph_err_d) begin
// First phase of 2-phase AHBL error response. Pass the exception along on // First phase of 2-phase AHBL error response. Pass the exception along on
// this cycle, and on the next cycle the trap entry will be asserted, // this cycle, and on the next cycle the trap entry will be asserted,