colin
/
Hazard3
1
0
Fork 0
Code Issues Pull Requests Packages Projects Releases Wiki Activity

Update readme

This commit is contained in:
Luke Wren 2022-08-22 09:25:37 +01:00
parent b90d12efed
commit f9dafa3867
1 changed files with 0 additions and 4 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

4
Readme.md
View File

@ -21,10 +21,6 @@ This repository also contains a compliant RISC-V Debug Module for Hazard3, which
There is an [example SoC integration](example_soc/soc/example_soc.v), showing how these components can be assembled to create a minimal system with a JTAG-enabled RISC-V processor, some RAM and a serial port. There is an [example SoC integration](example_soc/soc/example_soc.v), showing how these components can be assembled to create a minimal system with a JTAG-enabled RISC-V processor, some RAM and a serial port.
The following are planned for future implementation:
* Debug trigger unit (breakpoint-only)
Hazard3 is still under development. Hazard3 is still under development.
# Links to Specifications # Links to Specifications