colin
/
Hazard3
1
0
Fork 0
Code Issues Pull Requests Packages Projects Releases Wiki Activity

Add Xh3bextm instructions to rvcpp, and rename xh3b test to xh3bextm

This commit is contained in:
Luke Wren 2024-03-20 23:45:30 +00:00
parent 8cbf5fceee
commit fd584ea24b
2 changed files with 15 additions and 1 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

16
test/sim/rvcpp/rv.cpp
View File

@ -365,7 +365,8 @@ struct RVCore {
OPC_BRANCH = 0b11'000, OPC_BRANCH = 0b11'000,
OPC_JALR = 0b11'001, OPC_JALR = 0b11'001,
OPC_JAL = 0b11'011, OPC_JAL = 0b11'011,
OPC_SYSTEM = 0b11'100 OPC_SYSTEM = 0b11'100,
OPC_CUSTOM0 = 0b00'010
}; };
void step(MemBase32 &mem, bool trace=false) { void step(MemBase32 &mem, bool trace=false) {
@ -777,6 +778,19 @@ struct RVCore {
break; break;
} }
case OPC_CUSTOM0: {
if (RVOPC_MATCH(instr, H3_BEXTM)) {
uint size = GETBITS(instr, 28, 26) + 1;
rd_wdata = (rs1 >> (rs2 & 0x1f)) & ~(-1u << size);
} else if (RVOPC_MATCH(instr, H3_BEXTMI)) {
uint size = GETBITS(instr, 28, 26) + 1;
rd_wdata = (rs1 >> regnum_rs2) & ~(-1u << size);
} else {
exception_cause = XCAUSE_INSTR_ILLEGAL;
}
break;
}
default: default:
exception_cause = XCAUSE_INSTR_ILLEGAL; exception_cause = XCAUSE_INSTR_ILLEGAL;
break; break;

0
test/sim/sw_testcases/extension_xh3b.c → test/sim/sw_testcases/extension_xh3bextm.c
View File