Luke Wren
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04f138ae0e
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Fix mcontrol.execute not being writable. Enable hardware breakpoint debug tests: Hwpb1/2, JumpHBreak, TriggerExecuteInstant
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2022-08-23 00:05:30 +01:00 |
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Luke Wren
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91be98f2da
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Make rvpy IO output look exactly like tb_cxxrtl (bringing up embench)
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2022-07-06 23:53:11 +01:00 |
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Luke Wren
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27793b25a1
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Rebase riscv-tests against upstream, and pick up new semihosting file io test
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2022-07-04 00:45:20 +01:00 |
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Luke Wren
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e44d2e6f9e
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Add memory sampling to run-debug-tests. Add run-smp-debug-tests. Bump riscv-tests to get new SMP target, and a test fix for MemorySampleMixed
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2022-07-03 23:34:12 +01:00 |
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Luke Wren
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460fa0bb4a
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Fix run-isa-tests.sh to fail on first failed test. Fix bad environment trap routing causing ecall ISA test to hang. Make breakpoint test instant-pass when triggers aren't implemented.
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2022-05-28 17:22:28 +01:00 |
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Luke Wren
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4090f4eb24
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Initial bringup of riscv-tests. Pass 63 out of 66 applicable tests.gstat
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2022-05-28 15:01:27 +01:00 |
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Luke Wren
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632c61daba
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Rebase debug tests, pick up two new tests (both pass)
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2022-05-28 11:34:41 +01:00 |
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Luke Wren
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b655148148
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Bump riscv-tests for better PMP disable fix
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2022-05-27 21:36:54 +01:00 |
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Luke Wren
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d7787942e9
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Add two new tests to debug test list. Remainder are still non-applicable
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2022-05-26 00:47:08 +01:00 |
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Luke Wren
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a17b941e38
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Add U bit to misa, and fix some broken debug tests (no hazard3 bugs)
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2022-05-25 23:46:23 +01:00 |
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Luke Wren
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37f7588bad
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Fix hazard3 reset vector check value in debug tests
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2022-05-25 21:45:36 +01:00 |
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Luke Wren
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6d55cd2d55
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Consolidate openocd and bin-load testbenches
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2021-12-11 09:46:38 +00:00 |
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Luke Wren
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5db6c68c56
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Update riscv-tests for correct misa.x value
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2021-12-04 11:19:43 +00:00 |
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Luke Wren
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4d14203586
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Update riscv-tests fork for crash loop debug test
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2021-11-23 21:58:39 +00:00 |
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Luke Wren
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b0d11c0ab7
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Add RISC-V debug tests
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2021-07-22 17:50:04 +01:00 |