Luke Wren
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a17b941e38
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Add U bit to misa, and fix some broken debug tests (no hazard3 bugs)
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2022-05-25 23:46:23 +01:00 |
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Luke Wren
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37f7588bad
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Fix hazard3 reset vector check value in debug tests
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2022-05-25 21:45:36 +01:00 |
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Luke Wren
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6d55cd2d55
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Consolidate openocd and bin-load testbenches
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2021-12-11 09:46:38 +00:00 |
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Luke Wren
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5db6c68c56
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Update riscv-tests for correct misa.x value
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2021-12-04 11:19:43 +00:00 |
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Luke Wren
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4d14203586
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Update riscv-tests fork for crash loop debug test
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2021-11-23 21:58:39 +00:00 |
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Luke Wren
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b0d11c0ab7
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Add RISC-V debug tests
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2021-07-22 17:50:04 +01:00 |