4 Commits

Author	SHA1	Message	Date
Luke Wren	5193dfe477	Add separate define HAZARD3_ASSERTIONS for enabling internal assertions, ... and enable it only on the bus compliance model checks. Trying to make the solver's life easier in instruction_fetch_match.	2022-06-25 20:08:40 +01:00
Luke Wren	0a369efc06	Add single-port bus compliance. Fix adapter not re-arbitrating following an ERROR response, causing a squashed younger load-store to remain presented to the bus.	2021-12-18 15:41:05 +00:00
Luke Wren	449348f459	Fix bug where an IRQ can fire during load/store dphase, followed by dphase bus exception. ... Result was that the exception would sample the IRQ vector PC rather than the load/store instruction PC. Fix by fencing off on in-flight dphases before asserting the IRQ. This adds a cycle of jitter to IRQs, but is required for correct operation without adding a full exception-gathering pipeline.	2021-12-07 19:24:53 +00:00
Luke Wren	16dc905dce	Add simple formal bus properties check	2021-05-30 10:19:42 +01:00