Luke Wren
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8721bd3deb
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Add RISC-V timer to example soc, and tweak ULX3S config
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2022-10-07 03:11:36 +01:00 |
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Luke Wren
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f48177c644
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Tie off debug LEDs in ULX3S top level
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2022-09-05 00:37:44 +01:00 |
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Luke Wren
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d1b5f83b7a
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Beef up the ULX3S SoC again now that atomics aren't so disastrous for timing
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2021-12-18 02:41:50 +00:00 |
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Luke Wren
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b0d28447ab
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New license headers: DWTFPL -> Apache 2.0
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2021-12-13 23:23:40 +00:00 |
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Luke Wren
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924967ee72
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Back off ULX3S frequency to 40 MHz -- 50 works fine but fails to close after increasing RAM from 4k to 128k
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2021-07-25 13:41:04 +01:00 |
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Luke Wren
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6fcc74a043
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Add some instructions to Readme
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2021-07-24 11:53:08 +01:00 |
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Luke Wren
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115cb2c50f
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Tweaks to example soc configuration
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2021-07-23 23:08:23 +01:00 |
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Luke Wren
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2ae30183aa
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Working ECP5 debug, seems a bit slow but maybe just due to bitbanged FT231X JTAG.
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2021-07-23 18:32:47 +01:00 |