Luke Wren
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8e7ffb040c
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Comment typo
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2022-12-17 11:39:47 +00:00 |
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Luke Wren
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624d39669d
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Fix up new asserts in hazard3_power_ctrl. Add power signals to formal TBs.
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2022-08-29 19:20:09 +01:00 |
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Luke Wren
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d5cd3e0681
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Add SBA patch-through to 1-core wrapper.
Add SBA properties to bus compliance checks.
Hook up SBA in dual-core single-port debug tb.
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2022-07-03 15:17:44 +01:00 |
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Luke Wren
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0a369efc06
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Add single-port bus compliance. Fix adapter not re-arbitrating following an ERROR response, causing a squashed younger load-store to remain presented to the bus.
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2021-12-18 15:41:05 +00:00 |
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Luke Wren
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52d58fdee4
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Add keep wires for debug port on bus compliance tb
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2021-12-11 12:06:10 +00:00 |
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Luke Wren
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93be227d8a
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Add (currently failing) trap entry property. Fails when an IRQ arrives during a load/store data phase which subsequently excepts.
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2021-12-06 20:12:23 +00:00 |
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Luke Wren
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16dc905dce
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Add simple formal bus properties check
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2021-05-30 10:19:42 +01:00 |