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Author SHA1 Message Date
Luke Wren 449348f459 Fix bug where an IRQ can fire during load/store dphase, followed by dphase bus exception. 
Result was that the exception would sample the IRQ vector PC rather than the load/store instruction PC.
Fix by fencing off on in-flight dphases before asserting the IRQ. This adds a cycle of jitter
to IRQs, but is required for correct operation without adding a full exception-gathering pipeline.
 2021-12-07 19:24:53 +00:00
Luke Wren 16dc905dce Add simple formal bus properties check 2021-05-30 10:19:42 +01:00