6 Commits

Author	SHA1	Message	Date
Luke Wren	449348f459	Fix bug where an IRQ can fire during load/store dphase, followed by dphase bus exception. ... Result was that the exception would sample the IRQ vector PC rather than the load/store instruction PC. Fix by fencing off on in-flight dphases before asserting the IRQ. This adds a cycle of jitter to IRQs, but is required for correct operation without adding a full exception-gathering pipeline.	2021-12-07 19:24:53 +00:00
Luke Wren	dbc331dbb4	Add exclusives bus properties	2021-12-07 05:47:25 +00:00
Luke Wren	93be227d8a	Add (currently failing) trap entry property. Fails when an IRQ arrives during a load/store data phase which subsequently excepts.	2021-12-06 20:12:23 +00:00
Luke Wren	16dc905dce	Add simple formal bus properties check	2021-05-30 10:19:42 +01:00
Luke Wren	089bcc7c43	Typo	2021-05-29 23:24:18 +01:00
Luke Wren	90acfdcbe8	Organise test directory into formal and sim	2021-05-23 07:42:35 +01:00