3 Commits

Author	SHA1	Message	Date
Luke Wren	52d58fdee4	Add keep wires for debug port on bus compliance tb	2021-12-11 12:06:10 +00:00
Luke Wren	93be227d8a	Add (currently failing) trap entry property. Fails when an IRQ arrives during a load/store data phase which subsequently excepts.	2021-12-06 20:12:23 +00:00
Luke Wren	16dc905dce	Add simple formal bus properties check	2021-05-30 10:19:42 +01:00