2 Commits

Author	SHA1	Message	Date
Luke Wren	12851d3742	Bring mtvec vectoring modes in line with spec: all exceptions go to mtvec, IRQs are optionally vectored away from it if mtvec LSB is set	2021-05-30 19:52:46 +01:00
Luke Wren	90acfdcbe8	Organise test directory into formal and sim	2021-05-23 07:42:35 +01:00