8e7ffb040c
Comment typo
2022-12-17 11:39:47 +00:00
624d39669d
Fix up new asserts in hazard3_power_ctrl. Add power signals to formal TBs.
2022-08-29 19:20:09 +01:00
d5cd3e0681
Add SBA patch-through to 1-core wrapper.
...
Add SBA properties to bus compliance checks.
Hook up SBA in dual-core single-port debug tb.
2022-07-03 15:17:44 +01:00
5193dfe477
Add separate define HAZARD3_ASSERTIONS for enabling internal assertions,
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and enable it only on the bus compliance model checks. Trying to make
the solver's life easier in instruction_fetch_match.
2022-06-25 20:08:40 +01:00
0a369efc06
Add single-port bus compliance. Fix adapter not re-arbitrating following an ERROR response, causing a squashed younger load-store to remain presented to the bus.
2021-12-18 15:41:05 +00:00
52d58fdee4
Add keep wires for debug port on bus compliance tb
2021-12-11 12:06:10 +00:00
449348f459
Fix bug where an IRQ can fire during load/store dphase, followed by dphase bus exception.
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Result was that the exception would sample the IRQ vector PC rather than the load/store instruction PC.
Fix by fencing off on in-flight dphases before asserting the IRQ. This adds a cycle of jitter
to IRQs, but is required for correct operation without adding a full exception-gathering pipeline.
2021-12-07 19:24:53 +00:00
93be227d8a
Add (currently failing) trap entry property. Fails when an IRQ arrives during a load/store data phase which subsequently excepts.
2021-12-06 20:12:23 +00:00
16dc905dce
Add simple formal bus properties check
2021-05-30 10:19:42 +01:00
Luke Wren