2 Commits

Author	SHA1	Message	Date
Luke Wren	91be98f2da	Make rvpy IO output look exactly like tb_cxxrtl (bringing up embench)	2022-07-06 23:53:11 +01:00
Luke Wren	e44d2e6f9e	Add memory sampling to run-debug-tests. Add run-smp-debug-tests. Bump riscv-tests to get new SMP target, and a test fix for MemorySampleMixed	2022-07-03 23:34:12 +01:00