Luke Wren
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91be98f2da
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Make rvpy IO output look exactly like tb_cxxrtl (bringing up embench)
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2022-07-06 23:53:11 +01:00 |
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Luke Wren
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5a39d8b7e7
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Track minstret and mcycle separately now that the model is cycle-accurate
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2022-07-06 13:50:13 +01:00 |
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Luke Wren
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5dfe5cb62b
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Update rvpy to match current fastest config: stage 2 mul, single BTB entry on backward branches
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2022-07-06 13:49:51 +01:00 |
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Luke Wren
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d31b1708db
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Make rvpy cycle-accurate enough to get the correct Dhrystone score
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2022-06-09 01:34:37 +01:00 |
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Luke Wren
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5aca1381ac
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Couple of fixups for rvpy which I forgot to commit at some point
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2022-03-01 20:27:18 +00:00 |
Richard-Gordon
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375a6d60b7
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Correct mnemonic when logging unsigned sltiu instruction
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2021-10-08 12:02:37 +01:00 |
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Luke Wren
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90acfdcbe8
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Organise test directory into formal and sim
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2021-05-23 07:42:35 +01:00 |