Luke Wren
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e98d7b41ea
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Hook up power control signals on dual-core tb
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2023-03-22 00:34:19 +00:00 |
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Luke Wren
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dff278ea05
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Increase DTM idle cycle hint to 8 cycles -- see #6
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2022-10-19 21:11:18 +01:00 |
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Luke Wren
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874cb20910
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Add config headers to tb_cxxrtl instead of using defparams in Makefile
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2022-10-08 08:09:26 +01:00 |
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Luke Wren
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bf38d93d33
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Remove references to AHB-Lite, describe buses as (a subset of) AHB5
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2022-08-28 14:15:20 +01:00 |
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Luke Wren
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15cb21ae43
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First pass at implementing the new IRQ controls. Works well enough that the old tests pass :)
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2022-08-07 20:51:12 +01:00 |
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Luke Wren
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9e15cd3485
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Add standalone SBA-to-AHB shim, and make SBA off by default in the DM
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2022-07-03 15:30:33 +01:00 |
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Luke Wren
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d5cd3e0681
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Add SBA patch-through to 1-core wrapper.
Add SBA properties to bus compliance checks.
Hook up SBA in dual-core single-port debug tb.
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2022-07-03 15:17:44 +01:00 |
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Luke Wren
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8ef9d77be8
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Add 'everything but MHARTID' option to config_inst, to allow its reuse in multicore instantiations.
Use this to fix the multicore tb not instantiating cores with all parameters correct (e.g. U_MODE)
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2022-06-25 13:11:40 +01:00 |
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Luke Wren
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5ab60422ad
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Add minimal multicore launch code
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2021-12-17 01:24:11 +00:00 |
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Luke Wren
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01d9617f9c
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Add multicore tb integration file
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2021-12-17 00:41:23 +00:00 |