Luke Wren 5f4127948d Add a parameter to control register file reset, instead of the weird ifdef tree		2022-05-23 13:29:44 +01:00
..
fpga	Beef up the ULX3S SoC again now that atomics aren't so disastrous for timing	2021-12-18 02:41:50 +00:00
libfpga@9d50e12e01	Bump libfpga for correct bus error response from AHBL splitter in example SoC	2021-11-28 01:35:52 +00:00
soc	Add a parameter to control register file reset, instead of the weird ifdef tree	2022-05-23 13:29:44 +01:00
synth	Remove flash XIP from example_soc -- keep it simple and reclaim UART FTDI pins on iCEBreaker	2021-11-21 15:55:52 +00:00
icebreaker-openocd.cfg	Small code cleanup	2021-07-24 10:08:27 +01:00
ulx3s-openocd.cfg	Working ECP5 debug, seems a bit slow but maybe just due to bitbanged FT231X JTAG.	2021-07-23 18:32:47 +01:00