Luke Wren 6da0e12bbd Merge latest riscv-tests: updates for debug + ISA tests. ... Add a list of excluded tests, with reasons, to run-debug-tests.sh		2024-05-29 14:03:17 +01:00
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riscv-tests@7281064978	Merge latest riscv-tests: updates for debug + ISA tests.	2024-05-29 14:03:17 +01:00
debug.gtkw	Make rvpy IO output look exactly like tb_cxxrtl (bringing up embench)	2022-07-06 23:53:11 +01:00
run-debug-tests.sh	Merge latest riscv-tests: updates for debug + ISA tests.	2024-05-29 14:03:17 +01:00
run-isa-tests.sh	Fix run-isa-tests.sh to fail on first failed test. Fix bad environment trap routing causing ecall ISA test to hang. Make breakpoint test instant-pass when triggers aren't implemented.	2022-05-28 17:22:28 +01:00
run-smp-debug-tests.sh	Capture JTAG bitbang log from most recent SMP debug test.	2023-03-31 02:16:23 +01:00