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Hazard3/test/sim/tb_cxxrtl
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whitequark 12bf9bb570 Make CXXRTL testbench ~25% faster 2021-07-18 16:04:19 +01:00
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.gitignore Organise test directory into formal and sim 2021-05-23 07:42:35 +01:00
Makefile Make CXXRTL testbench ~25% faster 2021-07-18 16:04:19 +01:00
tb.cpp Double-step() after clock posedge to workaround CXXRTL port propagation issue 2021-07-18 16:03:53 +01:00