Hazard3/test/sim/tb_cxxrtl
Luke Wren 207566660d tb: handle both ports identically. Preparing for dual core 2021-12-17 00:04:00 +00:00
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.gitignore Organise test directory into formal and sim 2021-05-23 07:42:35 +01:00
Makefile Add test for identification CSRs vs expected values 2021-12-11 13:26:59 +00:00
compliance.cfg Consolidate openocd and bin-load testbenches 2021-12-11 09:46:38 +00:00
gdbinit Consolidate openocd and bin-load testbenches 2021-12-11 09:46:38 +00:00
multicore.gtkw tb: handle both ports identically. Preparing for dual core 2021-12-17 00:04:00 +00:00
openocd.cfg Consolidate openocd and bin-load testbenches 2021-12-11 09:46:38 +00:00
tb.cpp tb: handle both ports identically. Preparing for dual core 2021-12-17 00:04:00 +00:00
tb.f Consolidate openocd and bin-load testbenches 2021-12-11 09:46:38 +00:00
tb.v tb: handle both ports identically. Preparing for dual core 2021-12-17 00:04:00 +00:00
waves.gtkw Consolidate openocd and bin-load testbenches 2021-12-11 09:46:38 +00:00