Luke Wren 23b4dbe7f3 Redesign fetch queue: 2x32 + 3x16 -> 6x16. ... Should make it easier to support finer-grained flushing, and handle predicted branches cleanly.		2022-06-12 02:44:08 +01:00
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.gitignore	Add instruction fetch match check	2021-05-30 11:22:36 +01:00
Makefile	Add single-port bus compliance. Fix adapter not re-arbitrating following an ERROR response, causing a squashed younger load-store to remain presented to the bus.	2021-12-18 15:41:05 +00:00
disasm.py	Redesign fetch queue: 2x32 + 3x16 -> 6x16.	2022-06-12 02:44:08 +01:00
hazard3_formal_regression.vh	Redesign fetch queue: 2x32 + 3x16 -> 6x16.	2022-06-12 02:44:08 +01:00
tb.f	Add instruction fetch match check	2021-05-30 11:22:36 +01:00
tb.v	Add new bus signals on instruction_fetch_match/tb.v	2022-05-27 21:48:45 +01:00