Luke Wren 26d699e18c rvcpp simulator: fix bad regnum decode for c.slli outside of x8..x15		2023-04-01 06:02:45 +01:00
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bitmanip-random	Add Zbkb to bitmanip tests and regenerate vectors	2022-05-21 17:15:46 +01:00
common	Restore SW Makefiles to use whatever riscv32-unknown-elf toolchain is in PATH	2023-03-31 01:53:28 +01:00
coremark	Restore SW Makefiles to use whatever riscv32-unknown-elf toolchain is in PATH	2023-03-31 01:53:28 +01:00
dhrystone	Restore SW Makefiles to use whatever riscv32-unknown-elf toolchain is in PATH	2023-03-31 01:53:28 +01:00
embench	Update embench config and readme	2023-03-31 03:02:06 +01:00
hello_multicore	Add minimal multicore launch code	2021-12-17 01:24:11 +00:00
hellow	Restore SW Makefiles to use whatever riscv32-unknown-elf toolchain is in PATH	2023-03-31 01:53:28 +01:00
riscv-compliance	Fix +x permission of riscv-compliance/clean_all script	2023-04-01 04:42:15 +01:00
riscv-tests	Capture JTAG bitbang log from most recent SMP debug test.	2023-03-31 02:16:23 +01:00
rvcpp	rvcpp simulator: fix bad regnum decode for c.slli outside of x8..x15	2023-04-01 06:02:45 +01:00
rvpy	Make rvpy IO output look exactly like tb_cxxrtl (bringing up embench)	2022-07-06 23:53:11 +01:00
sw_testcases	Restore SW Makefiles to use whatever riscv32-unknown-elf toolchain is in PATH	2023-03-31 01:53:28 +01:00
tb_cxxrtl	tb_cxxrtl Makefile: make synthesis depend on config headers	2023-04-01 04:41:39 +01:00