Hazard3/test/sim/common
Luke Wren 2f6e98335f Add two new tests for IRQs-over-Zcmp, and fix a bug they found:
Interrupting the PC-setting step of a cm.popret (only) can sample the return target
as the exception return PC, which will cause the stack pointer adjust to be skipped
when returning from the IRQ. Fix this by making the PC-setting step uninterruptible

(note the PC-setting step is the instruction we execute first out of the group
of instructions specified in the Zc spec as being atomic wrt interrupts. This
does not itself imply that the PC-setting step is uninterruptible, it just
requires that when the PC-setting step retires, all following steps also retire.
However this is not sufficient given the special case logic that allows the jr
ra PC-setting step to execute before the final stack adjust as an optimisation.)
2023-11-03 21:12:21 +00:00
..
hazard3_csr.h Fix a couple of bugs in preemption priority update, add simple IRQ preemption test 2022-08-07 22:04:42 +01:00
hazard3_instr.h Implement block/unblock instructions, and fix questionable partial masking of sleep signals on exceptions. Add simple test for self-block/unblock with loopback in tb. 2022-08-29 14:52:01 +01:00
hazard3_irq.h Add two new tests for IRQs-over-Zcmp, and fix a bug they found: 2023-11-03 21:12:21 +00:00
init.S Add exclusives monitor to testbench 2021-12-17 17:03:35 +00:00
irq_dispatch.S Add test for IRQ force array 2022-08-09 23:38:14 +01:00
memmap.ld Add RISC-V debug tests 2021-07-22 17:50:04 +01:00
src_only_app.mk Silence useless linker rwx warning 2023-11-03 20:09:02 +00:00
tb_cxxrtl_io.h Add exclusives monitor to testbench 2021-12-17 17:03:35 +00:00